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ARM: 7325/1: fix v7 boot with lockdep enabled

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Bootup with lockdep enabled has been broken on v7 since b46c0f7465
("ARM: 7321/1: cache-v7: Disable preemption when reading CCSIDR").

This is because v7_setup (which is called very early during boot) calls
v7_flush_dcache_all, and the save_and_disable_irqs added by that patch
ends up attempting to call into lockdep C code (trace_hardirqs_off())
when we are in no position to execute it (no stack, MMU off).

Fix this by using a notrace variant of save_and_disable_irqs.  The code
already uses the notrace variant of restore_irqs.

Reviewed-by: Nicolas Pitre <nico@linaro.org>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: stable@vger.kernel.org
Signed-off-by: Rabin Vincent <rabin@rab.in>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Rabin Vincent 2012-02-15 16:01:42 +01:00 committed by Russell King
parent 6e2e340b59
commit 8e43a905dd
2 changed files with 6 additions and 1 deletions
repo.diff.show_diff_stats Download patch file Download diff file Expand all files Collapse all files

5
arch/arm/include/asm/assembler.h
View file

@ -137,6 +137,11 @@
disable_irq disable_irq
.endm .endm
.macro save_and_disable_irqs_notrace, oldcpsr
mrs \oldcpsr, cpsr
disable_irq_notrace
.endm
/* /*
* Restore interrupt state previously stored in a register. We don't * Restore interrupt state previously stored in a register. We don't
* guarantee that this will preserve the flags. * guarantee that this will preserve the flags.

2
arch/arm/mm/cache-v7.S
View file

@ -55,7 +55,7 @@ loop1:
cmp r1, #2 @ see what cache we have at this level cmp r1, #2 @ see what cache we have at this level
blt skip @ skip if no cache, or just i-cache blt skip @ skip if no cache, or just i-cache
#ifdef CONFIG_PREEMPT #ifdef CONFIG_PREEMPT
save_and_disable_irqs r9 @ make cssr&csidr read atomic save_and_disable_irqs_notrace r9 @ make cssr&csidr read atomic
#endif #endif
mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
isb @ isb to sych the new cssr&csidr isb @ isb to sych the new cssr&csidr