forked from mirrors/linux
		
	MIPS: Modify core io.h macros to account for the Octeon Errata Core-301.
Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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					 1 changed files with 14 additions and 0 deletions
				
			
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					@ -295,6 +295,12 @@ static inline void iounmap(const volatile void __iomem *addr)
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#undef __IS_KSEG1
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					#undef __IS_KSEG1
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}
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					}
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					#ifdef CONFIG_CPU_CAVIUM_OCTEON
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					#define war_octeon_io_reorder_wmb()  		wmb()
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					#else
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					#define war_octeon_io_reorder_wmb()		do { } while (0)
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					#endif
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#define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq)			\
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					#define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq)			\
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														\
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static inline void pfx##write##bwlq(type val,				\
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					static inline void pfx##write##bwlq(type val,				\
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					@ -303,6 +309,8 @@ static inline void pfx##write##bwlq(type val,				\
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	volatile type *__mem;						\
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						volatile type *__mem;						\
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	type __val;							\
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						type __val;							\
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														\
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						war_octeon_io_reorder_wmb();					\
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														\
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	__mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem));	\
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						__mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem));	\
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														\
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	__val = pfx##ioswab##bwlq(__mem, val);				\
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						__val = pfx##ioswab##bwlq(__mem, val);				\
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					@ -370,6 +378,8 @@ static inline void pfx##out##bwlq##p(type val, unsigned long port)	\
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	volatile type *__addr;						\
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						volatile type *__addr;						\
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	type __val;							\
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						type __val;							\
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														\
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						war_octeon_io_reorder_wmb();					\
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														\
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	__addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
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						__addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
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														\
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	__val = pfx##ioswab##bwlq(__addr, val);				\
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						__val = pfx##ioswab##bwlq(__addr, val);				\
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					@ -504,8 +514,12 @@ BUILDSTRING(q, u64)
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#endif
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					#endif
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					#ifdef CONFIG_CPU_CAVIUM_OCTEON
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					#define mmiowb() wmb()
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					#else
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/* Depends on MIPS II instruction set */
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					/* Depends on MIPS II instruction set */
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#define mmiowb() asm volatile ("sync" ::: "memory")
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					#define mmiowb() asm volatile ("sync" ::: "memory")
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					#endif
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static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
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					static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
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{
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					{
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