forked from mirrors/linux
phy: usb: Add USB2.0 phy driver for Sunplus SP7021
Add USB2.0 phy driver for Sunplus SP7021 Signed-off-by: Vincent Shih <vincent.sunplus@gmail.com> Link: https://lore.kernel.org/r/1658717052-26142-2-git-send-email-vincent.sunplus@gmail.com [vkoul: remove trailing line in driver file] Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Vincent Shih
Vinod Koul
parent
c8c5d5e89a
commit
99d9ccd973
6 changed files with 320 additions and 0 deletions
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@ -19490,6 +19490,14 @@ S: Maintained
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F: Documentation/devicetree/bindings/nvmem/sunplus,sp7021-ocotp.yaml
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F: drivers/nvmem/sunplus-ocotp.c
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SUNPLUS USB2 PHY DRIVER
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M: Vincent Shih <vincent.sunplus@gmail.com>
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L: linux-usb@vger.kernel.org
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S: Maintained
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F: drivers/phy/sunplus/Kconfig
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F: drivers/phy/sunplus/Makefile
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F: drivers/phy/sunplus/phy-sunplus-usb2.c
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SUNPLUS PWM DRIVER
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M: Hammer Hsieh <hammerh0314@gmail.com>
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S: Maintained
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@ -91,6 +91,7 @@ source "drivers/phy/rockchip/Kconfig"
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source "drivers/phy/samsung/Kconfig"
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source "drivers/phy/socionext/Kconfig"
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source "drivers/phy/st/Kconfig"
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source "drivers/phy/sunplus/Kconfig"
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source "drivers/phy/tegra/Kconfig"
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source "drivers/phy/ti/Kconfig"
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source "drivers/phy/intel/Kconfig"
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@ -31,6 +31,7 @@ obj-y += allwinner/ \
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samsung/ \
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socionext/ \
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st/ \
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sunplus/ \
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tegra/ \
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ti/ \
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xilinx/
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12
drivers/phy/sunplus/Kconfig
Normal file
12
drivers/phy/sunplus/Kconfig
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@ -0,0 +1,12 @@
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# SPDX-License-Identifier: GPL-2.0-only
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config PHY_SUNPLUS_USB
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tristate "Sunplus SP7021 USB 2.0 PHY driver"
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depends on OF && (SOC_SP7021 || COMPILE_TEST)
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select GENERIC_PHY
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help
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Enable this to support the USB 2.0 PHY on Sunplus SP7021
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SoC. The USB 2.0 PHY controller supports battery charger
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and synchronous signals, various power down modes including
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operating, partial and suspend modes, and high-speed,
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full-speed and low-speed data transfer.
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2
drivers/phy/sunplus/Makefile
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2
drivers/phy/sunplus/Makefile
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@ -0,0 +1,2 @@
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# SPDX-License-Identifier: GPL-2.0-only
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obj-$(CONFIG_PHY_SUNPLUS_USB) += phy-sunplus-usb2.o
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296
drivers/phy/sunplus/phy-sunplus-usb2.c
Normal file
296
drivers/phy/sunplus/phy-sunplus-usb2.c
Normal file
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@ -0,0 +1,296 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Sunplus SP7021 USB 2.0 phy driver
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*
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* Copyright (C) 2022 Sunplus Technology Inc., All rights reserved.
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*
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* Note 1 : non-posted write command for the registers accesses of
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* Sunplus SP7021.
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*
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/nvmem-consumer.h>
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#include <linux/of_platform.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#define HIGH_MASK_BITS GENMASK(31, 16)
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#define LOW_MASK_BITS GENMASK(15, 0)
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#define OTP_DISC_LEVEL_DEFAULT 0xd
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/* GROUP UPHY */
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#define CONFIG1 0x4
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#define J_HS_TX_PWRSAV BIT(5)
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#define CONFIG3 0xc
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#define J_FORCE_DISC_ON BIT(5)
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#define J_DEBUG_CTRL_ADDR_MACRO BIT(0)
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#define CONFIG7 0x1c
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#define J_DISC 0X1f
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#define CONFIG9 0x24
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#define J_ECO_PATH BIT(6)
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#define CONFIG16 0x40
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#define J_TBCWAIT_MASK GENMASK(6, 5)
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#define J_TBCWAIT_1P1_MS FIELD_PREP(J_TBCWAIT_MASK, 0)
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#define J_TVDM_SRC_DIS_MASK GENMASK(4, 3)
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#define J_TVDM_SRC_DIS_8P2_MS FIELD_PREP(J_TVDM_SRC_DIS_MASK, 3)
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#define J_TVDM_SRC_EN_MASK GENMASK(2, 1)
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#define J_TVDM_SRC_EN_1P6_MS FIELD_PREP(J_TVDM_SRC_EN_MASK, 0)
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#define J_BC_EN BIT(0)
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#define CONFIG17 0x44
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#define IBG_TRIM0_MASK GENMASK(7, 5)
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#define IBG_TRIM0_SSLVHT FIELD_PREP(IBG_TRIM0_MASK, 4)
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#define J_VDATREE_TRIM_MASK GENMASK(4, 1)
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#define J_VDATREE_TRIM_DEFAULT FIELD_PREP(J_VDATREE_TRIM_MASK, 9)
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#define CONFIG23 0x5c
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#define PROB_MASK GENMASK(5, 3)
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#define PROB FIELD_PREP(PROB_MASK, 7)
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/* GROUP MOON4 */
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#define UPHY_CONTROL0 0x0
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#define UPHY_CONTROL1 0x4
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#define UPHY_CONTROL2 0x8
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#define MO1_UPHY_RX_CLK_SEL BIT(6)
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#define MASK_MO1_UPHY_RX_CLK_SEL BIT(6 + 16)
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#define UPHY_CONTROL3 0xc
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#define MO1_UPHY_PLL_POWER_OFF_SEL BIT(7)
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#define MASK_MO1_UPHY_PLL_POWER_OFF_SEL BIT(7 + 16)
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#define MO1_UPHY_PLL_POWER_OFF BIT(3)
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#define MASK_UPHY_PLL_POWER_OFF BIT(3 + 16)
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struct sp_usbphy {
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struct device *dev;
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struct resource *phy_res_mem;
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struct resource *moon4_res_mem;
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struct reset_control *rstc;
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struct clk *phy_clk;
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void __iomem *phy_regs;
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void __iomem *moon4_regs;
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u32 disc_vol_addr_off;
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};
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static int update_disc_vol(struct sp_usbphy *usbphy)
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{
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struct nvmem_cell *cell;
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char *disc_name = "disc_vol";
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ssize_t otp_l = 0;
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char *otp_v;
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u32 val, set;
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cell = nvmem_cell_get(usbphy->dev, disc_name);
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if (IS_ERR_OR_NULL(cell)) {
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if (PTR_ERR(cell) == -EPROBE_DEFER)
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return -EPROBE_DEFER;
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}
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otp_v = nvmem_cell_read(cell, &otp_l);
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nvmem_cell_put(cell);
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if (otp_v) {
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set = *(otp_v + 1);
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set = (set << (sizeof(char) * 8)) | *otp_v;
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set = (set >> usbphy->disc_vol_addr_off) & J_DISC;
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}
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if (!otp_v || set == 0)
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set = OTP_DISC_LEVEL_DEFAULT;
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val = readl(usbphy->phy_regs + CONFIG7);
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val = (val & ~J_DISC) | set;
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writel(val, usbphy->phy_regs + CONFIG7);
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return 0;
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}
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static int sp_uphy_init(struct phy *phy)
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{
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struct sp_usbphy *usbphy = phy_get_drvdata(phy);
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u32 val;
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int ret;
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ret = clk_prepare_enable(usbphy->phy_clk);
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if (ret)
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goto err_clk;
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ret = reset_control_deassert(usbphy->rstc);
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if (ret)
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goto err_reset;
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/* Default value modification */
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writel(HIGH_MASK_BITS | 0x4002, usbphy->moon4_regs + UPHY_CONTROL0);
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writel(HIGH_MASK_BITS | 0x8747, usbphy->moon4_regs + UPHY_CONTROL1);
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/* disconnect voltage */
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ret = update_disc_vol(usbphy);
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if (ret < 0)
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return ret;
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/* board uphy 0 internal register modification for tid certification */
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val = readl(usbphy->phy_regs + CONFIG9);
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val &= ~(J_ECO_PATH);
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writel(val, usbphy->phy_regs + CONFIG9);
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val = readl(usbphy->phy_regs + CONFIG1);
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val &= ~(J_HS_TX_PWRSAV);
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writel(val, usbphy->phy_regs + CONFIG1);
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val = readl(usbphy->phy_regs + CONFIG23);
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val = (val & ~PROB) | PROB;
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writel(val, usbphy->phy_regs + CONFIG23);
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/* port 0 uphy clk fix */
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writel(MASK_MO1_UPHY_RX_CLK_SEL | MO1_UPHY_RX_CLK_SEL,
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usbphy->moon4_regs + UPHY_CONTROL2);
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/* battery charger */
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writel(J_TBCWAIT_1P1_MS | J_TVDM_SRC_DIS_8P2_MS | J_TVDM_SRC_EN_1P6_MS | J_BC_EN,
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usbphy->phy_regs + CONFIG16);
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writel(IBG_TRIM0_SSLVHT | J_VDATREE_TRIM_DEFAULT, usbphy->phy_regs + CONFIG17);
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/* chirp mode */
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writel(J_FORCE_DISC_ON | J_DEBUG_CTRL_ADDR_MACRO, usbphy->phy_regs + CONFIG3);
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return 0;
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err_reset:
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reset_control_assert(usbphy->rstc);
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err_clk:
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clk_disable_unprepare(usbphy->phy_clk);
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return ret;
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}
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static int sp_uphy_power_on(struct phy *phy)
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{
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struct sp_usbphy *usbphy = phy_get_drvdata(phy);
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u32 pll_pwr_on, pll_pwr_off;
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/* PLL power off/on twice */
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pll_pwr_off = (readl(usbphy->moon4_regs + UPHY_CONTROL3) & ~LOW_MASK_BITS)
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| MO1_UPHY_PLL_POWER_OFF_SEL | MO1_UPHY_PLL_POWER_OFF;
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pll_pwr_on = (readl(usbphy->moon4_regs + UPHY_CONTROL3) & ~LOW_MASK_BITS)
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| MO1_UPHY_PLL_POWER_OFF_SEL;
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writel(MASK_MO1_UPHY_PLL_POWER_OFF_SEL | MASK_UPHY_PLL_POWER_OFF | pll_pwr_off,
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usbphy->moon4_regs + UPHY_CONTROL3);
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mdelay(1);
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writel(MASK_MO1_UPHY_PLL_POWER_OFF_SEL | MASK_UPHY_PLL_POWER_OFF | pll_pwr_on,
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usbphy->moon4_regs + UPHY_CONTROL3);
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mdelay(1);
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writel(MASK_MO1_UPHY_PLL_POWER_OFF_SEL | MASK_UPHY_PLL_POWER_OFF | pll_pwr_off,
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usbphy->moon4_regs + UPHY_CONTROL3);
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mdelay(1);
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writel(MASK_MO1_UPHY_PLL_POWER_OFF_SEL | MASK_UPHY_PLL_POWER_OFF | pll_pwr_on,
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usbphy->moon4_regs + UPHY_CONTROL3);
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mdelay(1);
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writel(MASK_MO1_UPHY_PLL_POWER_OFF_SEL | MASK_UPHY_PLL_POWER_OFF | 0x0,
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usbphy->moon4_regs + UPHY_CONTROL3);
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return 0;
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}
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static int sp_uphy_power_off(struct phy *phy)
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{
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struct sp_usbphy *usbphy = phy_get_drvdata(phy);
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u32 pll_pwr_off;
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pll_pwr_off = (readl(usbphy->moon4_regs + UPHY_CONTROL3) & ~LOW_MASK_BITS)
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| MO1_UPHY_PLL_POWER_OFF_SEL | MO1_UPHY_PLL_POWER_OFF;
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writel(MASK_MO1_UPHY_PLL_POWER_OFF_SEL | MASK_UPHY_PLL_POWER_OFF | pll_pwr_off,
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usbphy->moon4_regs + UPHY_CONTROL3);
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mdelay(1);
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writel(MASK_MO1_UPHY_PLL_POWER_OFF_SEL | MASK_UPHY_PLL_POWER_OFF | 0x0,
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usbphy->moon4_regs + UPHY_CONTROL3);
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return 0;
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}
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static int sp_uphy_exit(struct phy *phy)
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{
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struct sp_usbphy *usbphy = phy_get_drvdata(phy);
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reset_control_assert(usbphy->rstc);
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clk_disable_unprepare(usbphy->phy_clk);
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return 0;
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}
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static const struct phy_ops sp_uphy_ops = {
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.init = sp_uphy_init,
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.power_on = sp_uphy_power_on,
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.power_off = sp_uphy_power_off,
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.exit = sp_uphy_exit,
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};
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static const struct of_device_id sp_uphy_dt_ids[] = {
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{.compatible = "sunplus,sp7021-usb2-phy", },
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{ }
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};
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MODULE_DEVICE_TABLE(of, sp_uphy_dt_ids);
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static int sp_usb_phy_probe(struct platform_device *pdev)
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{
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struct sp_usbphy *usbphy;
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struct phy_provider *phy_provider;
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struct phy *phy;
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int ret;
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usbphy = devm_kzalloc(&pdev->dev, sizeof(*usbphy), GFP_KERNEL);
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if (!usbphy)
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return -ENOMEM;
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usbphy->dev = &pdev->dev;
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usbphy->phy_res_mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
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usbphy->phy_regs = devm_ioremap_resource(&pdev->dev, usbphy->phy_res_mem);
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if (IS_ERR(usbphy->phy_regs))
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return PTR_ERR(usbphy->phy_regs);
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usbphy->moon4_res_mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "moon4");
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usbphy->moon4_regs = devm_ioremap(&pdev->dev, usbphy->moon4_res_mem->start,
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resource_size(usbphy->moon4_res_mem));
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if (IS_ERR(usbphy->moon4_regs))
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return PTR_ERR(usbphy->moon4_regs);
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usbphy->phy_clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(usbphy->phy_clk))
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return PTR_ERR(usbphy->phy_clk);
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usbphy->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
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if (IS_ERR(usbphy->rstc))
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return PTR_ERR(usbphy->rstc);
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of_property_read_u32(pdev->dev.of_node, "sunplus,disc-vol-addr-off",
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&usbphy->disc_vol_addr_off);
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phy = devm_phy_create(&pdev->dev, NULL, &sp_uphy_ops);
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if (IS_ERR(phy)) {
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ret = -PTR_ERR(phy);
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return ret;
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}
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phy_set_drvdata(phy, usbphy);
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phy_provider = devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate);
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return PTR_ERR_OR_ZERO(phy_provider);
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}
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static struct platform_driver sunplus_usb_phy_driver = {
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.probe = sp_usb_phy_probe,
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.driver = {
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.name = "sunplus-usb2-phy",
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.of_match_table = sp_uphy_dt_ids,
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},
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};
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module_platform_driver(sunplus_usb_phy_driver);
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MODULE_AUTHOR("Vincent Shih <vincent.shih@sunplus.com>");
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MODULE_DESCRIPTION("Sunplus USB 2.0 phy driver");
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MODULE_LICENSE("GPL");
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