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mmc: sunxi: Enable the new timings for the A64 MMC controllers

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The A64 MMC controllers need to set a "new timings" bit when a new rate is
set.

The actual meaning of that bit is not clear yet, but not setting it leads
to some corner-case issues, like the CMD53 failing, which is used to
implement SDIO packet aggregation.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Maxime Ripard 2017-01-27 22:38:36 +01:00 committed by Ulf Hansson
parent 860fdf89b9
commit 9a37e53e45
1 changed files with 6 additions and 0 deletions
repo.diff.show_diff_stats Download patch file Download diff file Expand all files Collapse all files

6
drivers/mmc/host/sunxi-mmc.c
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@ -253,6 +253,8 @@ struct sunxi_mmc_cfg {
/* does the IP block support autocalibration? */ /* does the IP block support autocalibration? */
bool can_calibrate; bool can_calibrate;
bool needs_new_timings;
}; };
struct sunxi_mmc_host { struct sunxi_mmc_host {
@ -779,6 +781,9 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,
} }
mmc_writel(host, REG_CLKCR, rval); mmc_writel(host, REG_CLKCR, rval);
if (host->cfg->needs_new_timings)
mmc_writel(host, REG_SD_NTSR, SDXC_2X_TIMING_MODE);
ret = sunxi_mmc_clk_set_phase(host, ios, rate); ret = sunxi_mmc_clk_set_phase(host, ios, rate);
if (ret) if (ret)
return ret; return ret;
@ -1076,6 +1081,7 @@ static const struct sunxi_mmc_cfg sun50i_a64_cfg = {
.idma_des_size_bits = 16, .idma_des_size_bits = 16,
.clk_delays = NULL, .clk_delays = NULL,
.can_calibrate = true, .can_calibrate = true,
.needs_new_timings = true,
}; };
static const struct of_device_id sunxi_mmc_of_match[] = { static const struct of_device_id sunxi_mmc_of_match[] = {