forked from mirrors/linux
drm/amdgpu: add pmu counters
adding perf event counters Signed-off-by: Jonathan Kim <Jonathan.Kim@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Jonathan Kim
Alex Deucher
parent
e4cf4bf5b8
commit
9c7c85f7ea
4 changed files with 324 additions and 1 deletions
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@ -54,7 +54,7 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
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amdgpu_gtt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o amdgpu_atomfirmware.o \
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amdgpu_vf_error.o amdgpu_sched.o amdgpu_debugfs.o amdgpu_ids.o \
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amdgpu_gmc.o amdgpu_xgmi.o amdgpu_csa.o amdgpu_ras.o amdgpu_vm_cpu.o \
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amdgpu_vm_sdma.o
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amdgpu_vm_sdma.o amdgpu_pmu.o
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# add asic specific block
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amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \
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@ -61,6 +61,7 @@
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#include "amdgpu_xgmi.h"
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#include "amdgpu_ras.h"
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#include "amdgpu_pmu.h"
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MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
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MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin");
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@ -2746,6 +2747,10 @@ int amdgpu_device_init(struct amdgpu_device *adev,
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return r;
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}
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r = amdgpu_pmu_init(adev);
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if (r)
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dev_err(adev->dev, "amdgpu_pmu_init failed\n");
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return 0;
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failed:
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@ -2814,6 +2819,7 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
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amdgpu_debugfs_regs_cleanup(adev);
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device_remove_file(adev->dev, &dev_attr_pcie_replay_count);
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amdgpu_ucode_sysfs_fini(adev);
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amdgpu_pmu_fini(adev);
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}
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280
drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c
Normal file
280
drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c
Normal file
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@ -0,0 +1,280 @@
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/*
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* Copyright 2019 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Author: Jonathan Kim <jonathan.kim@amd.com>
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*
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*/
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#include <linux/perf_event.h>
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#include <linux/init.h>
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#include "amdgpu.h"
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#include "amdgpu_pmu.h"
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#include "df_v3_6.h"
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#define PMU_NAME_SIZE 32
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/* record to keep track of pmu entry per pmu type per device */
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struct amdgpu_pmu_entry {
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struct list_head entry;
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struct amdgpu_device *adev;
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struct pmu pmu;
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unsigned int pmu_perf_type;
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};
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static LIST_HEAD(amdgpu_pmu_list);
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/* initialize perf counter */
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static int amdgpu_perf_event_init(struct perf_event *event)
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{
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struct hw_perf_event *hwc = &event->hw;
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/* test the event attr type check for PMU enumeration */
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if (event->attr.type != event->pmu->type)
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return -ENOENT;
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/* update the hw_perf_event struct with config data */
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hwc->conf = event->attr.config;
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return 0;
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}
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/* start perf counter */
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static void amdgpu_perf_start(struct perf_event *event, int flags)
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{
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struct hw_perf_event *hwc = &event->hw;
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struct amdgpu_pmu_entry *pe = container_of(event->pmu,
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struct amdgpu_pmu_entry,
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pmu);
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if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED)))
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return;
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WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
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hwc->state = 0;
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switch (pe->pmu_perf_type) {
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case PERF_TYPE_AMDGPU_DF:
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if (!(flags & PERF_EF_RELOAD))
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pe->adev->df_funcs->pmc_start(pe->adev, hwc->conf, 1);
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pe->adev->df_funcs->pmc_start(pe->adev, hwc->conf, 0);
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break;
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default:
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break;
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}
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perf_event_update_userpage(event);
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}
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/* read perf counter */
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static void amdgpu_perf_read(struct perf_event *event)
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{
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struct hw_perf_event *hwc = &event->hw;
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struct amdgpu_pmu_entry *pe = container_of(event->pmu,
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struct amdgpu_pmu_entry,
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pmu);
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u64 count, prev;
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do {
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prev = local64_read(&hwc->prev_count);
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switch (pe->pmu_perf_type) {
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case PERF_TYPE_AMDGPU_DF:
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pe->adev->df_funcs->pmc_get_count(pe->adev, hwc->conf,
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&count);
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break;
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default:
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count = 0;
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break;
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};
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} while (local64_cmpxchg(&hwc->prev_count, prev, count) != prev);
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local64_add(count - prev, &event->count);
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}
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/* stop perf counter */
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static void amdgpu_perf_stop(struct perf_event *event, int flags)
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{
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struct hw_perf_event *hwc = &event->hw;
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struct amdgpu_pmu_entry *pe = container_of(event->pmu,
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struct amdgpu_pmu_entry,
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pmu);
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if (hwc->state & PERF_HES_UPTODATE)
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return;
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switch (pe->pmu_perf_type) {
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case PERF_TYPE_AMDGPU_DF:
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pe->adev->df_funcs->pmc_stop(pe->adev, hwc->conf, 0);
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break;
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default:
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break;
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};
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WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
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hwc->state |= PERF_HES_STOPPED;
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if (hwc->state & PERF_HES_UPTODATE)
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return;
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amdgpu_perf_read(event);
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hwc->state |= PERF_HES_UPTODATE;
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}
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/* add perf counter */
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static int amdgpu_perf_add(struct perf_event *event, int flags)
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{
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struct hw_perf_event *hwc = &event->hw;
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int retval;
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struct amdgpu_pmu_entry *pe = container_of(event->pmu,
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struct amdgpu_pmu_entry,
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pmu);
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event->hw.state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
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switch (pe->pmu_perf_type) {
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case PERF_TYPE_AMDGPU_DF:
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retval = pe->adev->df_funcs->pmc_start(pe->adev, hwc->conf, 1);
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break;
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default:
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return 0;
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};
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if (retval)
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return retval;
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if (flags & PERF_EF_START)
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amdgpu_perf_start(event, PERF_EF_RELOAD);
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return retval;
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}
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/* delete perf counter */
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static void amdgpu_perf_del(struct perf_event *event, int flags)
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{
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struct hw_perf_event *hwc = &event->hw;
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struct amdgpu_pmu_entry *pe = container_of(event->pmu,
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struct amdgpu_pmu_entry,
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pmu);
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amdgpu_perf_stop(event, PERF_EF_UPDATE);
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switch (pe->pmu_perf_type) {
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case PERF_TYPE_AMDGPU_DF:
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pe->adev->df_funcs->pmc_stop(pe->adev, hwc->conf, 1);
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break;
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default:
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break;
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};
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perf_event_update_userpage(event);
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}
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/* vega20 pmus */
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/* init pmu tracking per pmu type */
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static int init_pmu_by_type(struct amdgpu_device *adev,
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const struct attribute_group *attr_groups[],
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char *pmu_type_name, char *pmu_file_prefix,
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unsigned int pmu_perf_type,
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unsigned int num_counters)
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{
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char pmu_name[PMU_NAME_SIZE];
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struct amdgpu_pmu_entry *pmu_entry;
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int ret = 0;
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pmu_entry = kzalloc(sizeof(struct amdgpu_pmu_entry), GFP_KERNEL);
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if (!pmu_entry)
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return -ENOMEM;
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pmu_entry->adev = adev;
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pmu_entry->pmu = (struct pmu){
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.event_init = amdgpu_perf_event_init,
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.add = amdgpu_perf_add,
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.del = amdgpu_perf_del,
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.start = amdgpu_perf_start,
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.stop = amdgpu_perf_stop,
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.read = amdgpu_perf_read,
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.task_ctx_nr = perf_invalid_context,
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};
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pmu_entry->pmu.attr_groups = attr_groups;
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pmu_entry->pmu_perf_type = pmu_perf_type;
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snprintf(pmu_name, PMU_NAME_SIZE, "%s_%d",
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pmu_file_prefix, adev->ddev->primary->index);
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ret = perf_pmu_register(&pmu_entry->pmu, pmu_name, -1);
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if (ret) {
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kfree(pmu_entry);
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pr_warn("Error initializing AMDGPU %s PMUs.\n", pmu_type_name);
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return ret;
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}
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pr_info("Detected AMDGPU %s Counters. # of Counters = %d.\n",
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pmu_type_name, num_counters);
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list_add_tail(&pmu_entry->entry, &amdgpu_pmu_list);
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return 0;
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}
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/* init amdgpu_pmu */
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int amdgpu_pmu_init(struct amdgpu_device *adev)
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{
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int ret = 0;
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switch (adev->asic_type) {
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case CHIP_VEGA20:
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/* init df */
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ret = init_pmu_by_type(adev, df_v3_6_attr_groups,
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"DF", "amdgpu_df", PERF_TYPE_AMDGPU_DF,
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DF_V3_6_MAX_COUNTERS);
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/* other pmu types go here*/
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break;
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default:
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return 0;
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}
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return 0;
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}
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/* destroy all pmu data associated with target device */
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void amdgpu_pmu_fini(struct amdgpu_device *adev)
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{
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struct amdgpu_pmu_entry *pe, *temp;
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list_for_each_entry_safe(pe, temp, &amdgpu_pmu_list, entry) {
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if (pe->adev == adev) {
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list_del(&pe->entry);
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perf_pmu_unregister(&pe->pmu);
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kfree(pe);
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}
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}
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}
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37
drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.h
Normal file
37
drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.h
Normal file
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@ -0,0 +1,37 @@
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/*
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* Copyright 2019 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Author: Jonathan Kim <jonathan.kim@amd.com>
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*
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*/
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#ifndef _AMDGPU_PMU_H_
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#define _AMDGPU_PMU_H_
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enum amdgpu_pmu_perf_type {
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PERF_TYPE_AMDGPU_DF = 0,
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PERF_TYPE_AMDGPU_MAX
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};
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int amdgpu_pmu_init(struct amdgpu_device *adev);
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void amdgpu_pmu_fini(struct amdgpu_device *adev);
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#endif /* _AMDGPU_PMU_H_ */
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