forked from mirrors/linux
mmc: cqhci: support for command queue enabled host
This patch adds CMDQ support for command-queue compatible hosts. Command queue is added in eMMC-5.1 specification. This enables the controller to process upto 32 requests at a time. Adrian Hunter contributed renaming to cqhci, recovery, suspend and resume, cqhci_off, cqhci_wait_for_idle, and external timeout handling. Signed-off-by: Asutosh Das <asutoshd@codeaurora.org> Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org> Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org> Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org> Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org> Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org> Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Venkat Gopalakrishnan
Ulf Hansson
parent
1e8e55b670
commit
a4080225f5
4 changed files with 1404 additions and 0 deletions
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@ -857,6 +857,19 @@ config MMC_SUNXI
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This selects support for the SD/MMC Host Controller on
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Allwinner sunxi SoCs.
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config MMC_CQHCI
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tristate "Command Queue Host Controller Interface support"
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depends on HAS_DMA
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help
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This selects the Command Queue Host Controller Interface (CQHCI)
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support present in host controllers of Qualcomm Technologies, Inc
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amongst others.
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This controller supports eMMC devices with command queue support.
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If you have a controller with this interface, say Y or M here.
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If unsure, say N.
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config MMC_TOSHIBA_PCI
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tristate "Toshiba Type A SD/MMC Card Interface Driver"
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depends on PCI
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@ -92,6 +92,7 @@ obj-$(CONFIG_MMC_SDHCI_ST) += sdhci-st.o
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obj-$(CONFIG_MMC_SDHCI_MICROCHIP_PIC32) += sdhci-pic32.o
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obj-$(CONFIG_MMC_SDHCI_BRCMSTB) += sdhci-brcmstb.o
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obj-$(CONFIG_MMC_SDHCI_OMAP) += sdhci-omap.o
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obj-$(CONFIG_MMC_CQHCI) += cqhci.o
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ifeq ($(CONFIG_CB710_DEBUG),y)
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CFLAGS-cb710-mmc += -DDEBUG
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1150
drivers/mmc/host/cqhci.c
Normal file
1150
drivers/mmc/host/cqhci.c
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File diff suppressed because it is too large
Load diff
240
drivers/mmc/host/cqhci.h
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240
drivers/mmc/host/cqhci.h
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@ -0,0 +1,240 @@
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/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef LINUX_MMC_CQHCI_H
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#define LINUX_MMC_CQHCI_H
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#include <linux/compiler.h>
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#include <linux/bitops.h>
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#include <linux/spinlock_types.h>
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#include <linux/types.h>
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#include <linux/completion.h>
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#include <linux/wait.h>
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#include <linux/irqreturn.h>
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#include <asm/io.h>
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/* registers */
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/* version */
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#define CQHCI_VER 0x00
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#define CQHCI_VER_MAJOR(x) (((x) & GENMASK(11, 8)) >> 8)
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#define CQHCI_VER_MINOR1(x) (((x) & GENMASK(7, 4)) >> 4)
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#define CQHCI_VER_MINOR2(x) ((x) & GENMASK(3, 0))
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/* capabilities */
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#define CQHCI_CAP 0x04
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/* configuration */
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#define CQHCI_CFG 0x08
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#define CQHCI_DCMD 0x00001000
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#define CQHCI_TASK_DESC_SZ 0x00000100
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#define CQHCI_ENABLE 0x00000001
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/* control */
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#define CQHCI_CTL 0x0C
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#define CQHCI_CLEAR_ALL_TASKS 0x00000100
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#define CQHCI_HALT 0x00000001
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/* interrupt status */
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#define CQHCI_IS 0x10
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#define CQHCI_IS_HAC BIT(0)
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#define CQHCI_IS_TCC BIT(1)
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#define CQHCI_IS_RED BIT(2)
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#define CQHCI_IS_TCL BIT(3)
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#define CQHCI_IS_MASK (CQHCI_IS_TCC | CQHCI_IS_RED)
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/* interrupt status enable */
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#define CQHCI_ISTE 0x14
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/* interrupt signal enable */
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#define CQHCI_ISGE 0x18
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/* interrupt coalescing */
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#define CQHCI_IC 0x1C
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#define CQHCI_IC_ENABLE BIT(31)
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#define CQHCI_IC_RESET BIT(16)
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#define CQHCI_IC_ICCTHWEN BIT(15)
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#define CQHCI_IC_ICCTH(x) ((x & 0x1F) << 8)
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#define CQHCI_IC_ICTOVALWEN BIT(7)
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#define CQHCI_IC_ICTOVAL(x) (x & 0x7F)
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/* task list base address */
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#define CQHCI_TDLBA 0x20
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/* task list base address upper */
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#define CQHCI_TDLBAU 0x24
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/* door-bell */
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#define CQHCI_TDBR 0x28
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/* task completion notification */
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#define CQHCI_TCN 0x2C
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/* device queue status */
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#define CQHCI_DQS 0x30
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/* device pending tasks */
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#define CQHCI_DPT 0x34
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/* task clear */
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#define CQHCI_TCLR 0x38
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/* send status config 1 */
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#define CQHCI_SSC1 0x40
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/* send status config 2 */
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#define CQHCI_SSC2 0x44
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/* response for dcmd */
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#define CQHCI_CRDCT 0x48
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/* response mode error mask */
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#define CQHCI_RMEM 0x50
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/* task error info */
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#define CQHCI_TERRI 0x54
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#define CQHCI_TERRI_C_INDEX(x) ((x) & GENMASK(5, 0))
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#define CQHCI_TERRI_C_TASK(x) (((x) & GENMASK(12, 8)) >> 8)
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#define CQHCI_TERRI_C_VALID(x) ((x) & BIT(15))
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#define CQHCI_TERRI_D_INDEX(x) (((x) & GENMASK(21, 16)) >> 16)
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#define CQHCI_TERRI_D_TASK(x) (((x) & GENMASK(28, 24)) >> 24)
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#define CQHCI_TERRI_D_VALID(x) ((x) & BIT(31))
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/* command response index */
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#define CQHCI_CRI 0x58
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/* command response argument */
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#define CQHCI_CRA 0x5C
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#define CQHCI_INT_ALL 0xF
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#define CQHCI_IC_DEFAULT_ICCTH 31
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#define CQHCI_IC_DEFAULT_ICTOVAL 1
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/* attribute fields */
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#define CQHCI_VALID(x) ((x & 1) << 0)
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#define CQHCI_END(x) ((x & 1) << 1)
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#define CQHCI_INT(x) ((x & 1) << 2)
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#define CQHCI_ACT(x) ((x & 0x7) << 3)
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/* data command task descriptor fields */
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#define CQHCI_FORCED_PROG(x) ((x & 1) << 6)
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#define CQHCI_CONTEXT(x) ((x & 0xF) << 7)
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#define CQHCI_DATA_TAG(x) ((x & 1) << 11)
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#define CQHCI_DATA_DIR(x) ((x & 1) << 12)
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#define CQHCI_PRIORITY(x) ((x & 1) << 13)
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#define CQHCI_QBAR(x) ((x & 1) << 14)
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#define CQHCI_REL_WRITE(x) ((x & 1) << 15)
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#define CQHCI_BLK_COUNT(x) ((x & 0xFFFF) << 16)
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#define CQHCI_BLK_ADDR(x) ((x & 0xFFFFFFFF) << 32)
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/* direct command task descriptor fields */
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#define CQHCI_CMD_INDEX(x) ((x & 0x3F) << 16)
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#define CQHCI_CMD_TIMING(x) ((x & 1) << 22)
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#define CQHCI_RESP_TYPE(x) ((x & 0x3) << 23)
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/* transfer descriptor fields */
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#define CQHCI_DAT_LENGTH(x) ((x & 0xFFFF) << 16)
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#define CQHCI_DAT_ADDR_LO(x) ((x & 0xFFFFFFFF) << 32)
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#define CQHCI_DAT_ADDR_HI(x) ((x & 0xFFFFFFFF) << 0)
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struct cqhci_host_ops;
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struct mmc_host;
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struct cqhci_slot;
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struct cqhci_host {
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const struct cqhci_host_ops *ops;
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void __iomem *mmio;
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struct mmc_host *mmc;
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spinlock_t lock;
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/* relative card address of device */
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unsigned int rca;
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/* 64 bit DMA */
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bool dma64;
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int num_slots;
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int qcnt;
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u32 dcmd_slot;
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u32 caps;
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#define CQHCI_TASK_DESC_SZ_128 0x1
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u32 quirks;
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#define CQHCI_QUIRK_SHORT_TXFR_DESC_SZ 0x1
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bool enabled;
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bool halted;
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bool init_done;
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bool activated;
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bool waiting_for_idle;
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bool recovery_halt;
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size_t desc_size;
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size_t data_size;
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u8 *desc_base;
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/* total descriptor size */
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u8 slot_sz;
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/* 64/128 bit depends on CQHCI_CFG */
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u8 task_desc_len;
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/* 64 bit on 32-bit arch, 128 bit on 64-bit */
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u8 link_desc_len;
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u8 *trans_desc_base;
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/* same length as transfer descriptor */
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u8 trans_desc_len;
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dma_addr_t desc_dma_base;
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dma_addr_t trans_desc_dma_base;
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struct completion halt_comp;
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wait_queue_head_t wait_queue;
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struct cqhci_slot *slot;
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};
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struct cqhci_host_ops {
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void (*dumpregs)(struct mmc_host *mmc);
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void (*write_l)(struct cqhci_host *host, u32 val, int reg);
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u32 (*read_l)(struct cqhci_host *host, int reg);
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void (*enable)(struct mmc_host *mmc);
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void (*disable)(struct mmc_host *mmc, bool recovery);
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};
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static inline void cqhci_writel(struct cqhci_host *host, u32 val, int reg)
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{
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if (unlikely(host->ops->write_l))
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host->ops->write_l(host, val, reg);
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else
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writel_relaxed(val, host->mmio + reg);
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}
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static inline u32 cqhci_readl(struct cqhci_host *host, int reg)
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{
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if (unlikely(host->ops->read_l))
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return host->ops->read_l(host, reg);
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else
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return readl_relaxed(host->mmio + reg);
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}
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struct platform_device;
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irqreturn_t cqhci_irq(struct mmc_host *mmc, u32 intmask, int cmd_error,
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int data_error);
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int cqhci_init(struct cqhci_host *cq_host, struct mmc_host *mmc, bool dma64);
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struct cqhci_host *cqhci_pltfm_init(struct platform_device *pdev);
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int cqhci_suspend(struct mmc_host *mmc);
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int cqhci_resume(struct mmc_host *mmc);
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#endif
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