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drm/amd: Avoid reading the VBIOS part number twice

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The VBIOS part number is read both in amdgpu_atom_parse() as well
as in atom_get_vbios_pn() and stored twice in the `struct atom_context`
structure. Remove the first unnecessary read and move the `pr_info`
line from that read into the second.

v2: squash in unused variable removal

Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Mario Limonciello 2023-07-18 13:02:58 -05:00 committed by Alex Deucher
parent 18cf073faa
commit adf64e2142
7 changed files with 22 additions and 34 deletions
repo.diff.show_diff_stats Download patch file Download diff file Expand all files Collapse all files

2
drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
View file

@ -1776,7 +1776,7 @@ static ssize_t amdgpu_atombios_get_vbios_version(struct device *dev,
struct amdgpu_device *adev = drm_to_adev(ddev); struct amdgpu_device *adev = drm_to_adev(ddev);
struct atom_context *ctx = adev->mode_info.atom_context; struct atom_context *ctx = adev->mode_info.atom_context;
return sysfs_emit(buf, "%s\n", ctx->vbios_version); return sysfs_emit(buf, "%s\n", ctx->vbios_pn);
} }
static DEVICE_ATTR(vbios_version, 0444, amdgpu_atombios_get_vbios_version, static DEVICE_ATTR(vbios_version, 0444, amdgpu_atombios_get_vbios_version,

20
drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
View file

@ -60,10 +60,10 @@ static bool is_fru_eeprom_supported(struct amdgpu_device *adev, u32 *fru_addr)
switch (adev->asic_type) { switch (adev->asic_type) {
case CHIP_VEGA20: case CHIP_VEGA20:
/* D161 and D163 are the VG20 server SKUs */ /* D161 and D163 are the VG20 server SKUs */
if (strnstr(atom_ctx->vbios_version, "D161", if (strnstr(atom_ctx->vbios_pn, "D161",
sizeof(atom_ctx->vbios_version)) || sizeof(atom_ctx->vbios_pn)) ||
strnstr(atom_ctx->vbios_version, "D163", strnstr(atom_ctx->vbios_pn, "D163",
sizeof(atom_ctx->vbios_version))) { sizeof(atom_ctx->vbios_pn))) {
if (fru_addr) if (fru_addr)
*fru_addr = FRU_EEPROM_MADDR_6; *fru_addr = FRU_EEPROM_MADDR_6;
return true; return true;
@ -72,16 +72,16 @@ static bool is_fru_eeprom_supported(struct amdgpu_device *adev, u32 *fru_addr)
} }
case CHIP_ALDEBARAN: case CHIP_ALDEBARAN:
/* All Aldebaran SKUs have an FRU */ /* All Aldebaran SKUs have an FRU */
if (!strnstr(atom_ctx->vbios_version, "D673", if (!strnstr(atom_ctx->vbios_pn, "D673",
sizeof(atom_ctx->vbios_version))) sizeof(atom_ctx->vbios_pn)))
if (fru_addr) if (fru_addr)
*fru_addr = FRU_EEPROM_MADDR_6; *fru_addr = FRU_EEPROM_MADDR_6;
return true; return true;
case CHIP_SIENNA_CICHLID: case CHIP_SIENNA_CICHLID:
if (strnstr(atom_ctx->vbios_version, "D603", if (strnstr(atom_ctx->vbios_pn, "D603",
sizeof(atom_ctx->vbios_version))) { sizeof(atom_ctx->vbios_pn))) {
if (strnstr(atom_ctx->vbios_version, "D603GLXE", if (strnstr(atom_ctx->vbios_pn, "D603GLXE",
sizeof(atom_ctx->vbios_version))) { sizeof(atom_ctx->vbios_pn))) {
return false; return false;
} else { } else {
if (fru_addr) if (fru_addr)

2
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
View file

@ -1722,7 +1722,7 @@ static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused)
seq_printf(m, "MES feature version: %u, firmware version: 0x%08x\n", seq_printf(m, "MES feature version: %u, firmware version: 0x%08x\n",
fw_info.feature, fw_info.ver); fw_info.feature, fw_info.ver);
seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version); seq_printf(m, "VBIOS version: %s\n", ctx->vbios_pn);
return 0; return 0;
} }

8
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
View file

@ -2442,10 +2442,10 @@ static void amdgpu_ras_get_quirks(struct amdgpu_device *adev)
if (!ctx) if (!ctx)
return; return;
if (strnstr(ctx->vbios_version, "D16406", if (strnstr(ctx->vbios_pn, "D16406",
sizeof(ctx->vbios_version)) || sizeof(ctx->vbios_pn)) ||
strnstr(ctx->vbios_version, "D36002", strnstr(ctx->vbios_pn, "D36002",
sizeof(ctx->vbios_version))) sizeof(ctx->vbios_pn)))
adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX); adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX);
} }

8
drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
View file

@ -194,9 +194,9 @@ static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev,
/* VEGA20 and ARCTURUS */ /* VEGA20 and ARCTURUS */
if (adev->asic_type == CHIP_VEGA20) if (adev->asic_type == CHIP_VEGA20)
control->i2c_address = EEPROM_I2C_MADDR_0; control->i2c_address = EEPROM_I2C_MADDR_0;
else if (strnstr(atom_ctx->vbios_version, else if (strnstr(atom_ctx->vbios_pn,
"D342", "D342",
sizeof(atom_ctx->vbios_version))) sizeof(atom_ctx->vbios_pn)))
control->i2c_address = EEPROM_I2C_MADDR_0; control->i2c_address = EEPROM_I2C_MADDR_0;
else else
control->i2c_address = EEPROM_I2C_MADDR_4; control->i2c_address = EEPROM_I2C_MADDR_4;
@ -205,8 +205,8 @@ static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev,
control->i2c_address = EEPROM_I2C_MADDR_0; control->i2c_address = EEPROM_I2C_MADDR_0;
return true; return true;
case IP_VERSION(13, 0, 2): case IP_VERSION(13, 0, 2):
if (strnstr(atom_ctx->vbios_version, "D673", if (strnstr(atom_ctx->vbios_pn, "D673",
sizeof(atom_ctx->vbios_version))) sizeof(atom_ctx->vbios_pn)))
control->i2c_address = EEPROM_I2C_MADDR_4; control->i2c_address = EEPROM_I2C_MADDR_4;
else else
control->i2c_address = EEPROM_I2C_MADDR_0; control->i2c_address = EEPROM_I2C_MADDR_0;

14
drivers/gpu/drm/amd/amdgpu/atom.c
View file

@ -1438,6 +1438,8 @@ static void atom_get_vbios_pn(struct atom_context *ctx)
ctx->vbios_pn[count] = 0; ctx->vbios_pn[count] = 0;
} }
pr_info("ATOM BIOS: %s\n", ctx->vbios_pn);
} }
static void atom_get_vbios_version(struct atom_context *ctx) static void atom_get_vbios_version(struct atom_context *ctx)
@ -1460,11 +1462,9 @@ struct atom_context *amdgpu_atom_parse(struct card_info *card, void *bios)
int base; int base;
struct atom_context *ctx = struct atom_context *ctx =
kzalloc(sizeof(struct atom_context), GFP_KERNEL); kzalloc(sizeof(struct atom_context), GFP_KERNEL);
char *str;
struct _ATOM_ROM_HEADER *atom_rom_header; struct _ATOM_ROM_HEADER *atom_rom_header;
struct _ATOM_MASTER_DATA_TABLE *master_table; struct _ATOM_MASTER_DATA_TABLE *master_table;
struct _ATOM_FIRMWARE_INFO *atom_fw_info; struct _ATOM_FIRMWARE_INFO *atom_fw_info;
u16 idx;
if (!ctx) if (!ctx)
return NULL; return NULL;
@ -1502,16 +1502,6 @@ struct atom_context *amdgpu_atom_parse(struct card_info *card, void *bios)
return NULL; return NULL;
} }
idx = CU16(ATOM_ROM_PART_NUMBER_PTR);
if (idx == 0)
idx = 0x80;
str = CSTR(idx);
if (*str != '\0') {
pr_info("ATOM BIOS: %s\n", str);
strlcpy(ctx->vbios_version, str, sizeof(ctx->vbios_version));
}
atom_rom_header = (struct _ATOM_ROM_HEADER *)CSTR(base); atom_rom_header = (struct _ATOM_ROM_HEADER *)CSTR(base);
if (atom_rom_header->usMasterDataTableOffset != 0) { if (atom_rom_header->usMasterDataTableOffset != 0) {
master_table = (struct _ATOM_MASTER_DATA_TABLE *) master_table = (struct _ATOM_MASTER_DATA_TABLE *)

2
drivers/gpu/drm/amd/amdgpu/atom.h
View file

@ -33,7 +33,6 @@ struct drm_device;
#define ATOM_ATI_MAGIC_PTR 0x30 #define ATOM_ATI_MAGIC_PTR 0x30
#define ATOM_ATI_MAGIC " 761295520" #define ATOM_ATI_MAGIC " 761295520"
#define ATOM_ROM_TABLE_PTR 0x48 #define ATOM_ROM_TABLE_PTR 0x48
#define ATOM_ROM_PART_NUMBER_PTR 0x6E
#define ATOM_ROM_MAGIC "ATOM" #define ATOM_ROM_MAGIC "ATOM"
#define ATOM_ROM_MAGIC_PTR 4 #define ATOM_ROM_MAGIC_PTR 4
@ -143,7 +142,6 @@ struct atom_context {
int io_mode; int io_mode;
uint32_t *scratch; uint32_t *scratch;
int scratch_size_bytes; int scratch_size_bytes;
char vbios_version[20];
uint8_t name[STRLEN_LONG]; uint8_t name[STRLEN_LONG];
uint8_t vbios_pn[STRLEN_LONG]; uint8_t vbios_pn[STRLEN_LONG];