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igc: Add qbv_config_change_errors counter

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Add ConfigChangeError(qbv_config_change_errors) when user try to set the
AdminBaseTime to past value while the current GCL is still running.

The ConfigChangeError counter should not be increased when a gate control
list is scheduled into the future.

User can use "ethtool -S <interface> | grep qbv_config_change_errors"
command to check the counter values.

Signed-off-by: Muhammad Husaini Zulkifli <muhammad.husaini.zulkifli@intel.com>
Tested-by: Naama Meir <naamax.meir@linux.intel.com>
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
This commit is contained in:
Muhammad Husaini Zulkifli 2023-02-16 10:07:31 +08:00 committed by Tony Nguyen
parent 36e5e391a2
commit ae4fe46983
4 changed files with 15 additions and 0 deletions
repo.diff.show_diff_stats Download patch file Download diff file Expand all files Collapse all files

1
drivers/net/ethernet/intel/igc/igc.h
View file

@ -185,6 +185,7 @@ struct igc_adapter {
ktime_t base_time; ktime_t base_time;
ktime_t cycle_time; ktime_t cycle_time;
bool qbv_enable; bool qbv_enable;
u32 qbv_config_change_errors;
/* OS defined structs */ /* OS defined structs */
struct pci_dev *pdev; struct pci_dev *pdev;

1
drivers/net/ethernet/intel/igc/igc_ethtool.c
View file

@ -67,6 +67,7 @@ static const struct igc_stats igc_gstrings_stats[] = {
IGC_STAT("rx_hwtstamp_cleared", rx_hwtstamp_cleared), IGC_STAT("rx_hwtstamp_cleared", rx_hwtstamp_cleared),
IGC_STAT("tx_lpi_counter", stats.tlpic), IGC_STAT("tx_lpi_counter", stats.tlpic),
IGC_STAT("rx_lpi_counter", stats.rlpic), IGC_STAT("rx_lpi_counter", stats.rlpic),
IGC_STAT("qbv_config_change_errors", qbv_config_change_errors),
}; };
#define IGC_NETDEV_STAT(_net_stat) { \ #define IGC_NETDEV_STAT(_net_stat) { \

1
drivers/net/ethernet/intel/igc/igc_main.c
View file

@ -6049,6 +6049,7 @@ static int igc_tsn_clear_schedule(struct igc_adapter *adapter)
adapter->base_time = 0; adapter->base_time = 0;
adapter->cycle_time = NSEC_PER_SEC; adapter->cycle_time = NSEC_PER_SEC;
adapter->qbv_config_change_errors = 0;
for (i = 0; i < adapter->num_tx_queues; i++) { for (i = 0; i < adapter->num_tx_queues; i++) {
struct igc_ring *ring = adapter->tx_ring[i]; struct igc_ring *ring = adapter->tx_ring[i];

12
drivers/net/ethernet/intel/igc/igc_tsn.c
View file

@ -114,6 +114,7 @@ static int igc_tsn_disable_offload(struct igc_adapter *adapter)
static int igc_tsn_enable_offload(struct igc_adapter *adapter) static int igc_tsn_enable_offload(struct igc_adapter *adapter)
{ {
struct igc_hw *hw = &adapter->hw; struct igc_hw *hw = &adapter->hw;
bool tsn_mode_reconfig = false;
u32 tqavctrl, baset_l, baset_h; u32 tqavctrl, baset_l, baset_h;
u32 sec, nsec, cycle; u32 sec, nsec, cycle;
ktime_t base_time, systim; ktime_t base_time, systim;
@ -226,6 +227,10 @@ static int igc_tsn_enable_offload(struct igc_adapter *adapter)
} }
tqavctrl = rd32(IGC_TQAVCTRL) & ~IGC_TQAVCTRL_FUTSCDDIS; tqavctrl = rd32(IGC_TQAVCTRL) & ~IGC_TQAVCTRL_FUTSCDDIS;
if (tqavctrl & IGC_TQAVCTRL_TRANSMIT_MODE_TSN)
tsn_mode_reconfig = true;
tqavctrl |= IGC_TQAVCTRL_TRANSMIT_MODE_TSN | IGC_TQAVCTRL_ENHANCED_QAV; tqavctrl |= IGC_TQAVCTRL_TRANSMIT_MODE_TSN | IGC_TQAVCTRL_ENHANCED_QAV;
cycle = adapter->cycle_time; cycle = adapter->cycle_time;
@ -239,6 +244,13 @@ static int igc_tsn_enable_offload(struct igc_adapter *adapter)
s64 n = div64_s64(ktime_sub_ns(systim, base_time), cycle); s64 n = div64_s64(ktime_sub_ns(systim, base_time), cycle);
base_time = ktime_add_ns(base_time, (n + 1) * cycle); base_time = ktime_add_ns(base_time, (n + 1) * cycle);
/* Increase the counter if scheduling into the past while
* Gate Control List (GCL) is running.
*/
if ((rd32(IGC_BASET_H) || rd32(IGC_BASET_L)) &&
tsn_mode_reconfig)
adapter->qbv_config_change_errors++;
} else { } else {
/* According to datasheet section 7.5.2.9.3.3, FutScdDis bit /* According to datasheet section 7.5.2.9.3.3, FutScdDis bit
* has to be configured before the cycle time and base time. * has to be configured before the cycle time and base time.