forked from mirrors/linux
net: mscc: ocelot: switch from {,un}set to {,un}assign for tag_8021q CPU ports
There is a desire for the felix driver to gain support for multiple tag_8021q CPU ports, but the current model prevents it. This is because ocelot_apply_bridge_fwd_mask() only takes into consideration whether a port is a tag_8021q CPU port, but not whose CPU port it is. We need a model where we can have a direct affinity between an ocelot port and a tag_8021q CPU port. This serves as the basis for multiple CPU ports. Declare a "dsa_8021q_cpu" backpointer in struct ocelot_port which encodes that affinity. Repurpose the "ocelot_set_dsa_8021q_cpu" API to "ocelot_assign_dsa_8021q_cpu" to express the change of paradigm. Note that this change makes the first practical use of the new ocelot_port->index field in ocelot_port_unassign_dsa_8021q_cpu(), where we need to remove the old tag_8021q CPU port from the reserved VLAN range. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Vladimir Oltean
David S. Miller
parent
8c166acb60
commit
c295f9831f
4 changed files with 93 additions and 69 deletions
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@ -414,21 +414,18 @@ static const struct felix_tag_proto_ops felix_tag_npi_proto_ops = {
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static int felix_tag_8021q_setup(struct dsa_switch *ds)
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{
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struct ocelot *ocelot = ds->priv;
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struct dsa_port *dp, *cpu_dp;
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struct dsa_port *dp;
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int err;
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err = dsa_tag_8021q_register(ds, htons(ETH_P_8021AD));
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if (err)
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return err;
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dsa_switch_for_each_cpu_port(cpu_dp, ds) {
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ocelot_port_set_dsa_8021q_cpu(ocelot, cpu_dp->index);
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dsa_switch_for_each_user_port(dp, ds)
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ocelot_port_assign_dsa_8021q_cpu(ocelot, dp->index,
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dp->cpu_dp->index);
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/* TODO we could support multiple CPU ports in tag_8021q mode */
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break;
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}
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dsa_switch_for_each_available_port(dp, ds) {
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dsa_switch_for_each_available_port(dp, ds)
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/* This overwrites ocelot_init():
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* Do not forward BPDU frames to the CPU port module,
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* for 2 reasons:
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@ -442,7 +439,6 @@ static int felix_tag_8021q_setup(struct dsa_switch *ds)
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ocelot_write_gix(ocelot,
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ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0),
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ANA_PORT_CPU_FWD_BPDU_CFG, dp->index);
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}
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/* The ownership of the CPU port module's queues might have just been
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* transferred to the tag_8021q tagger from the NPI-based tagger.
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@ -459,9 +455,9 @@ static int felix_tag_8021q_setup(struct dsa_switch *ds)
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static void felix_tag_8021q_teardown(struct dsa_switch *ds)
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{
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struct ocelot *ocelot = ds->priv;
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struct dsa_port *dp, *cpu_dp;
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struct dsa_port *dp;
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dsa_switch_for_each_available_port(dp, ds) {
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dsa_switch_for_each_available_port(dp, ds)
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/* Restore the logic from ocelot_init:
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* do not forward BPDU frames to the front ports.
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*/
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@ -469,14 +465,9 @@ static void felix_tag_8021q_teardown(struct dsa_switch *ds)
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ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff),
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ANA_PORT_CPU_FWD_BPDU_CFG,
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dp->index);
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}
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dsa_switch_for_each_cpu_port(cpu_dp, ds) {
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ocelot_port_unset_dsa_8021q_cpu(ocelot, cpu_dp->index);
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/* TODO we could support multiple CPU ports in tag_8021q mode */
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break;
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}
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dsa_switch_for_each_user_port(dp, ds)
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ocelot_port_unassign_dsa_8021q_cpu(ocelot, dp->index);
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dsa_tag_8021q_unregister(ds);
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}
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@ -2162,7 +2162,8 @@ static void vsc9959_cut_through_fwd(struct ocelot *ocelot)
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if (ocelot->npi >= 0)
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mask |= BIT(ocelot->npi);
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else
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mask |= ocelot_get_dsa_8021q_cpu_mask(ocelot);
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mask |= ocelot_port_assigned_dsa_8021q_cpu_mask(ocelot,
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port);
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}
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/* Calculate the minimum link speed, among the ports that are
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@ -2046,6 +2046,37 @@ static int ocelot_bond_get_id(struct ocelot *ocelot, struct net_device *bond)
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return __ffs(bond_mask);
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}
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static u32 ocelot_dsa_8021q_cpu_assigned_ports(struct ocelot *ocelot,
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struct ocelot_port *cpu)
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{
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u32 mask = 0;
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int port;
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for (port = 0; port < ocelot->num_phys_ports; port++) {
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struct ocelot_port *ocelot_port = ocelot->ports[port];
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if (!ocelot_port)
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continue;
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if (ocelot_port->dsa_8021q_cpu == cpu)
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mask |= BIT(port);
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}
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return mask;
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}
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u32 ocelot_port_assigned_dsa_8021q_cpu_mask(struct ocelot *ocelot, int port)
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{
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struct ocelot_port *ocelot_port = ocelot->ports[port];
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struct ocelot_port *cpu_port = ocelot_port->dsa_8021q_cpu;
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if (!cpu_port)
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return 0;
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return BIT(cpu_port->index);
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}
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EXPORT_SYMBOL_GPL(ocelot_port_assigned_dsa_8021q_cpu_mask);
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u32 ocelot_get_bridge_fwd_mask(struct ocelot *ocelot, int src_port)
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{
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struct ocelot_port *ocelot_port = ocelot->ports[src_port];
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@ -2075,28 +2106,8 @@ u32 ocelot_get_bridge_fwd_mask(struct ocelot *ocelot, int src_port)
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}
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EXPORT_SYMBOL_GPL(ocelot_get_bridge_fwd_mask);
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u32 ocelot_get_dsa_8021q_cpu_mask(struct ocelot *ocelot)
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{
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u32 mask = 0;
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int port;
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for (port = 0; port < ocelot->num_phys_ports; port++) {
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struct ocelot_port *ocelot_port = ocelot->ports[port];
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if (!ocelot_port)
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continue;
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if (ocelot_port->is_dsa_8021q_cpu)
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mask |= BIT(port);
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}
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return mask;
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}
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EXPORT_SYMBOL_GPL(ocelot_get_dsa_8021q_cpu_mask);
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static void ocelot_apply_bridge_fwd_mask(struct ocelot *ocelot, bool joining)
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{
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unsigned long cpu_fwd_mask;
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int port;
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lockdep_assert_held(&ocelot->fwd_domain_lock);
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@ -2108,15 +2119,6 @@ static void ocelot_apply_bridge_fwd_mask(struct ocelot *ocelot, bool joining)
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if (joining && ocelot->ops->cut_through_fwd)
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ocelot->ops->cut_through_fwd(ocelot);
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/* If a DSA tag_8021q CPU exists, it needs to be included in the
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* regular forwarding path of the front ports regardless of whether
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* those are bridged or standalone.
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* If DSA tag_8021q is not used, this returns 0, which is fine because
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* the hardware-based CPU port module can be a destination for packets
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* even if it isn't part of PGID_SRC.
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*/
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cpu_fwd_mask = ocelot_get_dsa_8021q_cpu_mask(ocelot);
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/* Apply FWD mask. The loop is needed to add/remove the current port as
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* a source for the other ports.
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*/
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@ -2129,17 +2131,19 @@ static void ocelot_apply_bridge_fwd_mask(struct ocelot *ocelot, bool joining)
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mask = 0;
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} else if (ocelot_port->is_dsa_8021q_cpu) {
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/* The DSA tag_8021q CPU ports need to be able to
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* forward packets to all other ports except for
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* themselves
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* forward packets to all ports assigned to them.
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*/
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mask = GENMASK(ocelot->num_phys_ports - 1, 0);
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mask &= ~cpu_fwd_mask;
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mask = ocelot_dsa_8021q_cpu_assigned_ports(ocelot,
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ocelot_port);
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} else if (ocelot_port->bridge) {
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struct net_device *bond = ocelot_port->bond;
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mask = ocelot_get_bridge_fwd_mask(ocelot, port);
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mask |= cpu_fwd_mask;
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mask &= ~BIT(port);
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mask |= ocelot_port_assigned_dsa_8021q_cpu_mask(ocelot,
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port);
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if (bond)
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mask &= ~ocelot_get_bond_mask(ocelot, bond);
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} else {
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@ -2147,7 +2151,8 @@ static void ocelot_apply_bridge_fwd_mask(struct ocelot *ocelot, bool joining)
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* ports (if those exist), or to the hardware CPU port
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* module otherwise.
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*/
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mask = cpu_fwd_mask;
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mask = ocelot_port_assigned_dsa_8021q_cpu_mask(ocelot,
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port);
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}
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ocelot_write_rix(ocelot, mask, ANA_PGID_PGID, PGID_SRC + port);
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@ -2191,43 +2196,66 @@ static void ocelot_update_pgid_cpu(struct ocelot *ocelot)
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ocelot_write_rix(ocelot, pgid_cpu, ANA_PGID_PGID, PGID_CPU);
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}
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void ocelot_port_set_dsa_8021q_cpu(struct ocelot *ocelot, int port)
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void ocelot_port_assign_dsa_8021q_cpu(struct ocelot *ocelot, int port,
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int cpu)
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{
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struct ocelot_port *cpu_port = ocelot->ports[cpu];
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u16 vid;
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mutex_lock(&ocelot->fwd_domain_lock);
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ocelot->ports[port]->is_dsa_8021q_cpu = true;
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ocelot->ports[port]->dsa_8021q_cpu = cpu_port;
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for (vid = OCELOT_RSV_VLAN_RANGE_START; vid < VLAN_N_VID; vid++)
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ocelot_vlan_member_add(ocelot, port, vid, true);
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if (!cpu_port->is_dsa_8021q_cpu) {
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cpu_port->is_dsa_8021q_cpu = true;
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ocelot_update_pgid_cpu(ocelot);
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for (vid = OCELOT_RSV_VLAN_RANGE_START; vid < VLAN_N_VID; vid++)
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ocelot_vlan_member_add(ocelot, cpu, vid, true);
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ocelot_update_pgid_cpu(ocelot);
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}
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ocelot_apply_bridge_fwd_mask(ocelot, true);
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mutex_unlock(&ocelot->fwd_domain_lock);
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}
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EXPORT_SYMBOL_GPL(ocelot_port_set_dsa_8021q_cpu);
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EXPORT_SYMBOL_GPL(ocelot_port_assign_dsa_8021q_cpu);
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void ocelot_port_unset_dsa_8021q_cpu(struct ocelot *ocelot, int port)
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void ocelot_port_unassign_dsa_8021q_cpu(struct ocelot *ocelot, int port)
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{
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struct ocelot_port *cpu_port = ocelot->ports[port]->dsa_8021q_cpu;
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bool keep = false;
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u16 vid;
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int p;
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mutex_lock(&ocelot->fwd_domain_lock);
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ocelot->ports[port]->is_dsa_8021q_cpu = false;
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ocelot->ports[port]->dsa_8021q_cpu = NULL;
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for (vid = OCELOT_RSV_VLAN_RANGE_START; vid < VLAN_N_VID; vid++)
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ocelot_vlan_member_del(ocelot, port, vid);
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for (p = 0; p < ocelot->num_phys_ports; p++) {
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if (!ocelot->ports[p])
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continue;
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ocelot_update_pgid_cpu(ocelot);
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if (ocelot->ports[p]->dsa_8021q_cpu == cpu_port) {
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keep = true;
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break;
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}
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}
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if (!keep) {
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cpu_port->is_dsa_8021q_cpu = false;
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for (vid = OCELOT_RSV_VLAN_RANGE_START; vid < VLAN_N_VID; vid++)
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ocelot_vlan_member_del(ocelot, cpu_port->index, vid);
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ocelot_update_pgid_cpu(ocelot);
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}
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ocelot_apply_bridge_fwd_mask(ocelot, true);
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mutex_unlock(&ocelot->fwd_domain_lock);
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}
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EXPORT_SYMBOL_GPL(ocelot_port_unset_dsa_8021q_cpu);
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EXPORT_SYMBOL_GPL(ocelot_port_unassign_dsa_8021q_cpu);
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void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state)
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{
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@ -654,6 +654,8 @@ struct ocelot_mirror {
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int to;
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};
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struct ocelot_port;
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struct ocelot_port {
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struct ocelot *ocelot;
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@ -662,6 +664,8 @@ struct ocelot_port {
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struct net_device *bond;
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struct net_device *bridge;
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struct ocelot_port *dsa_8021q_cpu;
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/* VLAN that untagged frames are classified to, on ingress */
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const struct ocelot_bridge_vlan *pvid_vlan;
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@ -865,8 +869,9 @@ void ocelot_deinit(struct ocelot *ocelot);
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void ocelot_init_port(struct ocelot *ocelot, int port);
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void ocelot_deinit_port(struct ocelot *ocelot, int port);
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void ocelot_port_set_dsa_8021q_cpu(struct ocelot *ocelot, int port);
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void ocelot_port_unset_dsa_8021q_cpu(struct ocelot *ocelot, int port);
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void ocelot_port_assign_dsa_8021q_cpu(struct ocelot *ocelot, int port, int cpu);
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void ocelot_port_unassign_dsa_8021q_cpu(struct ocelot *ocelot, int port);
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u32 ocelot_port_assigned_dsa_8021q_cpu_mask(struct ocelot *ocelot, int port);
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/* DSA callbacks */
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void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data);
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@ -878,7 +883,6 @@ void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs);
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int ocelot_port_vlan_filtering(struct ocelot *ocelot, int port, bool enabled,
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struct netlink_ext_ack *extack);
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void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state);
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u32 ocelot_get_dsa_8021q_cpu_mask(struct ocelot *ocelot);
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u32 ocelot_get_bridge_fwd_mask(struct ocelot *ocelot, int src_port);
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int ocelot_port_pre_bridge_flags(struct ocelot *ocelot, int port,
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struct switchdev_brport_flags val);
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