forked from mirrors/linux
PCI: designware: Make driver arch-agnostic
Previously, dw_pcie_host_init() created the PCI host bridge with pci_common_init_dev(), an ARM-specific function that supplies the ARM- specific pci_sys_data structure as the PCI "sysdata". Make pcie-designware.c arch-agnostic by reimplementing the functionality of pci_common_init_dev() directly in dw_pcie_host_init(). Note that this changes the bridge sysdata from the ARM pci_sys_data to the DesignWare pcie_port structure. This doesn't affect the ARM sysdata users because they are all specific to non-DesignWare host bridges, which will still have pci_sys_data. [bhelgaas: changelog] Tested-by: James Morse <james.morse@arm.com> Tested-by: Gabriel Fernandez <gabriel.fernandez@st.com> Tested-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
This commit is contained in:
Zhou Wang
Bjorn Helgaas
parent
b3a72384fe
commit
cbce790059
2 changed files with 39 additions and 92 deletions
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@ -69,16 +69,7 @@
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#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
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#define PCIE_ATU_UPPER_TARGET 0x91C
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static struct hw_pci dw_pci;
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static unsigned long global_io_offset;
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static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys)
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{
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BUG_ON(!sys->private_data);
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return sys->private_data;
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}
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static struct pci_ops dw_pcie_ops;
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int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val)
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{
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@ -267,7 +258,7 @@ static void dw_pcie_msi_set_irq(struct pcie_port *pp, int irq)
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static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos)
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{
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int irq, pos0, i;
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struct pcie_port *pp = sys_to_pcie(msi_desc_to_pci_sysdata(desc));
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struct pcie_port *pp = (struct pcie_port *) msi_desc_to_pci_sysdata(desc);
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pos0 = bitmap_find_free_region(pp->msi_irq_in_use, MAX_MSI_IRQS,
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order_base_2(no_irqs));
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@ -333,7 +324,7 @@ static int dw_msi_setup_irq(struct msi_controller *chip, struct pci_dev *pdev,
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struct msi_desc *desc)
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{
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int irq, pos;
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struct pcie_port *pp = sys_to_pcie(pdev->bus->sysdata);
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struct pcie_port *pp = pdev->bus->sysdata;
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if (desc->msi_attrib.is_msix)
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return -EINVAL;
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@ -353,7 +344,7 @@ static int dw_msi_setup_irqs(struct msi_controller *chip, struct pci_dev *pdev,
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#ifdef CONFIG_PCI_MSI
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int irq, pos;
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struct msi_desc *desc;
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struct pcie_port *pp = sys_to_pcie(pdev->bus->sysdata);
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struct pcie_port *pp = pdev->bus->sysdata;
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/* MSI-X interrupts are not supported */
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if (type == PCI_CAP_ID_MSIX)
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@ -378,7 +369,7 @@ static void dw_msi_teardown_irq(struct msi_controller *chip, unsigned int irq)
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{
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struct irq_data *data = irq_get_irq_data(irq);
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struct msi_desc *msi = irq_data_get_msi_desc(data);
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struct pcie_port *pp = sys_to_pcie(msi_desc_to_pci_sysdata(msi));
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struct pcie_port *pp = (struct pcie_port *) msi_desc_to_pci_sysdata(msi);
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clear_irq_range(pp, irq, 1, data->hwirq);
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}
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@ -414,6 +405,7 @@ int dw_pcie_host_init(struct pcie_port *pp)
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{
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struct device_node *np = pp->dev->of_node;
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struct platform_device *pdev = to_platform_device(pp->dev);
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struct pci_bus *bus, *child;
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struct resource *cfg_res;
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u32 val;
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int i, ret;
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@ -442,14 +434,13 @@ int dw_pcie_host_init(struct pcie_port *pp)
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pp->io->name = "I/O";
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pp->io_size = resource_size(pp->io);
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pp->io_bus_addr = pp->io->start - win->offset;
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pp->io->start = max_t(resource_size_t, PCIBIOS_MIN_IO,
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pp->io_bus_addr +
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global_io_offset);
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pp->io->end = min_t(resource_size_t, IO_SPACE_LIMIT,
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pp->io_bus_addr + pp->io_size +
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global_io_offset - 1);
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ret = pci_remap_iospace(pp->io, pp->io_base);
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if (ret) {
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dev_warn(pp->dev, "error %d: failed to map resource %pR\n",
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ret, pp->io);
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continue;
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}
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pp->io_base = pp->io->start;
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pp->io_base_tmp = pp->io->start;
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break;
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case IORESOURCE_MEM:
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pp->mem = win->res;
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@ -541,15 +532,35 @@ int dw_pcie_host_init(struct pcie_port *pp)
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val |= PORT_LOGIC_SPEED_CHANGE;
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dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
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#ifdef CONFIG_PCI_MSI
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dw_pcie_msi_chip.dev = pp->dev;
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pp->root_bus_nr = pp->busn->start;
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if (IS_ENABLED(CONFIG_PCI_MSI)) {
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bus = pci_scan_root_bus_msi(pp->dev, pp->root_bus_nr,
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&dw_pcie_ops, pp, &res,
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&dw_pcie_msi_chip);
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dw_pcie_msi_chip.dev = pp->dev;
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} else
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bus = pci_scan_root_bus(pp->dev, pp->root_bus_nr, &dw_pcie_ops,
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pp, &res);
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if (!bus)
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return -ENOMEM;
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if (pp->ops->scan_bus)
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pp->ops->scan_bus(pp);
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#ifdef CONFIG_ARM
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/* support old dtbs that incorrectly describe IRQs */
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pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
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#endif
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dw_pci.nr_controllers = 1;
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dw_pci.private_data = (void **)&pp;
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if (!pci_has_flag(PCI_PROBE_ONLY)) {
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pci_bus_size_bridges(bus);
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pci_bus_assign_resources(bus);
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pci_common_init_dev(pp->dev, &dw_pci);
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list_for_each_entry(child, &bus->children, node)
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pcie_bus_configure_settings(child);
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}
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pci_bus_add_devices(bus);
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return 0;
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}
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@ -647,7 +658,7 @@ static int dw_pcie_valid_config(struct pcie_port *pp,
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static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
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int size, u32 *val)
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{
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struct pcie_port *pp = sys_to_pcie(bus->sysdata);
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struct pcie_port *pp = bus->sysdata;
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int ret;
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if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) {
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@ -671,7 +682,7 @@ static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
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static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
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int where, int size, u32 val)
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{
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struct pcie_port *pp = sys_to_pcie(bus->sysdata);
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struct pcie_port *pp = bus->sysdata;
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int ret;
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if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0)
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@ -695,69 +706,6 @@ static struct pci_ops dw_pcie_ops = {
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.write = dw_pcie_wr_conf,
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};
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static int dw_pcie_setup(int nr, struct pci_sys_data *sys)
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{
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struct pcie_port *pp;
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pp = sys_to_pcie(sys);
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if (global_io_offset < SZ_1M && pp->io_size > 0) {
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sys->io_offset = global_io_offset - pp->io_bus_addr;
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pci_ioremap_io(global_io_offset, pp->io_base_tmp);
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global_io_offset += SZ_64K;
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pci_add_resource_offset(&sys->resources, pp->io,
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sys->io_offset);
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}
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sys->mem_offset = pp->mem->start - pp->mem_bus_addr;
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pci_add_resource_offset(&sys->resources, pp->mem, sys->mem_offset);
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pci_add_resource(&sys->resources, pp->busn);
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return 1;
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}
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static struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys)
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{
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struct pci_bus *bus;
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struct pcie_port *pp = sys_to_pcie(sys);
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pp->root_bus_nr = sys->busnr;
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if (IS_ENABLED(CONFIG_PCI_MSI))
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bus = pci_scan_root_bus_msi(pp->dev, sys->busnr, &dw_pcie_ops,
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sys, &sys->resources,
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&dw_pcie_msi_chip);
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else
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bus = pci_scan_root_bus(pp->dev, sys->busnr, &dw_pcie_ops,
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sys, &sys->resources);
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if (!bus)
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return NULL;
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if (bus && pp->ops->scan_bus)
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pp->ops->scan_bus(pp);
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return bus;
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}
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static int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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struct pcie_port *pp = sys_to_pcie(dev->bus->sysdata);
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int irq;
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irq = of_irq_parse_and_map_pci(dev, slot, pin);
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if (!irq)
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irq = pp->irq;
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return irq;
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}
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static struct hw_pci dw_pci = {
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.setup = dw_pcie_setup,
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.scan = dw_pcie_scan_bus,
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.map_irq = dw_pcie_map_irq,
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};
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void dw_pcie_setup_rc(struct pcie_port *pp)
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{
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u32 val;
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@ -33,7 +33,6 @@ struct pcie_port {
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void __iomem *va_cfg1_base;
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u32 cfg1_size;
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resource_size_t io_base;
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resource_size_t io_base_tmp;
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phys_addr_t io_bus_addr;
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u32 io_size;
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u64 mem_base;
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