forked from mirrors/linux
fpga: add an initial KUnit suite for the FPGA Manager
The suite tests the basic behaviors of the FPGA Manager including programming using a single contiguous buffer and a scatter gather table. Signed-off-by: Marco Pagani <marpagan@redhat.com> Acked-by: Xu Yilun <yilun.xu@intel.com> Link: https://lore.kernel.org/r/20230718130304.87048-2-marpagan@redhat.com Signed-off-by: Xu Yilun <yilun.xu@intel.com>
This commit is contained in:
Marco Pagani
Xu Yilun
parent
840208392d
commit
ccbc1c3021
1 changed files with 327 additions and 0 deletions
327
drivers/fpga/tests/fpga-mgr-test.c
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327
drivers/fpga/tests/fpga-mgr-test.c
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// SPDX-License-Identifier: GPL-2.0
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/*
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* KUnit test for the FPGA Manager
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*
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* Copyright (C) 2023 Red Hat, Inc.
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*
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* Author: Marco Pagani <marpagan@redhat.com>
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*/
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#include <kunit/test.h>
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#include <linux/device.h>
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#include <linux/fpga/fpga-mgr.h>
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#include <linux/module.h>
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#include <linux/scatterlist.h>
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#include <linux/types.h>
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#define HEADER_FILL 'H'
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#define IMAGE_FILL 'P'
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#define IMAGE_BLOCK 1024
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#define HEADER_SIZE IMAGE_BLOCK
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#define IMAGE_SIZE (IMAGE_BLOCK * 4)
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struct mgr_stats {
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bool header_match;
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bool image_match;
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u32 seq_num;
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u32 op_parse_header_seq;
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u32 op_write_init_seq;
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u32 op_write_seq;
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u32 op_write_sg_seq;
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u32 op_write_complete_seq;
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enum fpga_mgr_states op_parse_header_state;
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enum fpga_mgr_states op_write_init_state;
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enum fpga_mgr_states op_write_state;
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enum fpga_mgr_states op_write_sg_state;
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enum fpga_mgr_states op_write_complete_state;
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};
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struct mgr_ctx {
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struct fpga_image_info *img_info;
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struct fpga_manager *mgr;
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struct platform_device *pdev;
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struct mgr_stats stats;
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};
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/**
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* init_test_buffer() - Allocate and initialize a test image in a buffer.
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* @test: KUnit test context object.
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* @count: image size in bytes.
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*
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* Return: pointer to the newly allocated image.
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*/
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static char *init_test_buffer(struct kunit *test, size_t count)
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{
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char *buf;
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KUNIT_ASSERT_GE(test, count, HEADER_SIZE);
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buf = kunit_kzalloc(test, count, GFP_KERNEL);
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KUNIT_ASSERT_NOT_ERR_OR_NULL(test, buf);
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memset(buf, HEADER_FILL, HEADER_SIZE);
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memset(buf + HEADER_SIZE, IMAGE_FILL, count - HEADER_SIZE);
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return buf;
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}
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/*
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* Check the image header. Do not return an error code if the image check fails
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* since, in this case, it is a failure of the FPGA manager itself, not this
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* op that tests it.
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*/
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static int op_parse_header(struct fpga_manager *mgr, struct fpga_image_info *info,
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const char *buf, size_t count)
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{
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struct mgr_stats *stats = mgr->priv;
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size_t i;
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stats->op_parse_header_state = mgr->state;
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stats->op_parse_header_seq = stats->seq_num++;
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/* Set header_size and data_size for later */
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info->header_size = HEADER_SIZE;
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info->data_size = info->count - HEADER_SIZE;
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stats->header_match = true;
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for (i = 0; i < info->header_size; i++) {
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if (buf[i] != HEADER_FILL) {
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stats->header_match = false;
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break;
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}
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}
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return 0;
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}
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static int op_write_init(struct fpga_manager *mgr, struct fpga_image_info *info,
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const char *buf, size_t count)
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{
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struct mgr_stats *stats = mgr->priv;
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stats->op_write_init_state = mgr->state;
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stats->op_write_init_seq = stats->seq_num++;
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return 0;
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}
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/*
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* Check the image data. As with op_parse_header, do not return an error code
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* if the image check fails.
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*/
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static int op_write(struct fpga_manager *mgr, const char *buf, size_t count)
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{
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struct mgr_stats *stats = mgr->priv;
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size_t i;
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stats->op_write_state = mgr->state;
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stats->op_write_seq = stats->seq_num++;
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stats->image_match = true;
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for (i = 0; i < count; i++) {
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if (buf[i] != IMAGE_FILL) {
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stats->image_match = false;
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break;
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}
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}
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return 0;
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}
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/*
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* Check the image data, but first skip the header since write_sg will get
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* the whole image in sg_table. As with op_parse_header, do not return an
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* error code if the image check fails.
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*/
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static int op_write_sg(struct fpga_manager *mgr, struct sg_table *sgt)
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{
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struct mgr_stats *stats = mgr->priv;
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struct sg_mapping_iter miter;
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char *img;
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size_t i;
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stats->op_write_sg_state = mgr->state;
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stats->op_write_sg_seq = stats->seq_num++;
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stats->image_match = true;
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sg_miter_start(&miter, sgt->sgl, sgt->nents, SG_MITER_FROM_SG);
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if (!sg_miter_skip(&miter, HEADER_SIZE)) {
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stats->image_match = false;
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goto out;
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}
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while (sg_miter_next(&miter)) {
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img = miter.addr;
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for (i = 0; i < miter.length; i++) {
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if (img[i] != IMAGE_FILL) {
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stats->image_match = false;
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goto out;
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}
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}
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}
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out:
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sg_miter_stop(&miter);
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return 0;
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}
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static int op_write_complete(struct fpga_manager *mgr, struct fpga_image_info *info)
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{
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struct mgr_stats *stats = mgr->priv;
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stats->op_write_complete_state = mgr->state;
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stats->op_write_complete_seq = stats->seq_num++;
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return 0;
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}
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/*
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* Fake FPGA manager that implements all ops required to check the programming
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* sequence using a single contiguous buffer and a scatter gather table.
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*/
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static const struct fpga_manager_ops fake_mgr_ops = {
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.skip_header = true,
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.parse_header = op_parse_header,
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.write_init = op_write_init,
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.write = op_write,
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.write_sg = op_write_sg,
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.write_complete = op_write_complete,
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};
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static void fpga_mgr_test_get(struct kunit *test)
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{
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struct mgr_ctx *ctx = test->priv;
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struct fpga_manager *mgr;
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mgr = fpga_mgr_get(&ctx->pdev->dev);
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KUNIT_EXPECT_PTR_EQ(test, mgr, ctx->mgr);
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fpga_mgr_put(ctx->mgr);
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}
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static void fpga_mgr_test_lock(struct kunit *test)
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{
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struct mgr_ctx *ctx = test->priv;
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int ret;
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ret = fpga_mgr_lock(ctx->mgr);
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KUNIT_EXPECT_EQ(test, ret, 0);
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ret = fpga_mgr_lock(ctx->mgr);
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KUNIT_EXPECT_EQ(test, ret, -EBUSY);
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fpga_mgr_unlock(ctx->mgr);
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}
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/* Check the programming sequence using an image in a buffer */
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static void fpga_mgr_test_img_load_buf(struct kunit *test)
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{
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struct mgr_ctx *ctx = test->priv;
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char *img_buf;
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int ret;
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img_buf = init_test_buffer(test, IMAGE_SIZE);
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ctx->img_info->count = IMAGE_SIZE;
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ctx->img_info->buf = img_buf;
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ret = fpga_mgr_load(ctx->mgr, ctx->img_info);
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KUNIT_EXPECT_EQ(test, ret, 0);
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KUNIT_EXPECT_TRUE(test, ctx->stats.header_match);
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KUNIT_EXPECT_TRUE(test, ctx->stats.image_match);
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KUNIT_EXPECT_EQ(test, ctx->stats.op_parse_header_state, FPGA_MGR_STATE_PARSE_HEADER);
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KUNIT_EXPECT_EQ(test, ctx->stats.op_write_init_state, FPGA_MGR_STATE_WRITE_INIT);
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KUNIT_EXPECT_EQ(test, ctx->stats.op_write_state, FPGA_MGR_STATE_WRITE);
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KUNIT_EXPECT_EQ(test, ctx->stats.op_write_complete_state, FPGA_MGR_STATE_WRITE_COMPLETE);
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KUNIT_EXPECT_EQ(test, ctx->stats.op_write_init_seq, ctx->stats.op_parse_header_seq + 1);
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KUNIT_EXPECT_EQ(test, ctx->stats.op_write_seq, ctx->stats.op_parse_header_seq + 2);
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KUNIT_EXPECT_EQ(test, ctx->stats.op_write_complete_seq, ctx->stats.op_parse_header_seq + 3);
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}
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/* Check the programming sequence using an image in a scatter gather table */
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static void fpga_mgr_test_img_load_sgt(struct kunit *test)
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{
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struct mgr_ctx *ctx = test->priv;
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struct sg_table *sgt;
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char *img_buf;
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int ret;
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img_buf = init_test_buffer(test, IMAGE_SIZE);
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sgt = kunit_kzalloc(test, sizeof(*sgt), GFP_KERNEL);
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ret = sg_alloc_table(sgt, 1, GFP_KERNEL);
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KUNIT_ASSERT_EQ(test, ret, 0);
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sg_init_one(sgt->sgl, img_buf, IMAGE_SIZE);
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ctx->img_info->sgt = sgt;
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ret = fpga_mgr_load(ctx->mgr, ctx->img_info);
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KUNIT_EXPECT_EQ(test, ret, 0);
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KUNIT_EXPECT_TRUE(test, ctx->stats.header_match);
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KUNIT_EXPECT_TRUE(test, ctx->stats.image_match);
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KUNIT_EXPECT_EQ(test, ctx->stats.op_parse_header_state, FPGA_MGR_STATE_PARSE_HEADER);
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KUNIT_EXPECT_EQ(test, ctx->stats.op_write_init_state, FPGA_MGR_STATE_WRITE_INIT);
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KUNIT_EXPECT_EQ(test, ctx->stats.op_write_sg_state, FPGA_MGR_STATE_WRITE);
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KUNIT_EXPECT_EQ(test, ctx->stats.op_write_complete_state, FPGA_MGR_STATE_WRITE_COMPLETE);
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KUNIT_EXPECT_EQ(test, ctx->stats.op_write_init_seq, ctx->stats.op_parse_header_seq + 1);
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KUNIT_EXPECT_EQ(test, ctx->stats.op_write_sg_seq, ctx->stats.op_parse_header_seq + 2);
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KUNIT_EXPECT_EQ(test, ctx->stats.op_write_complete_seq, ctx->stats.op_parse_header_seq + 3);
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sg_free_table(ctx->img_info->sgt);
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}
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static int fpga_mgr_test_init(struct kunit *test)
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{
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struct mgr_ctx *ctx;
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ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
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KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx);
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ctx->pdev = platform_device_register_simple("mgr_pdev", PLATFORM_DEVID_AUTO, NULL, 0);
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KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx->pdev);
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ctx->mgr = devm_fpga_mgr_register(&ctx->pdev->dev, "Fake FPGA Manager", &fake_mgr_ops,
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&ctx->stats);
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KUNIT_ASSERT_FALSE(test, IS_ERR_OR_NULL(ctx->mgr));
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ctx->img_info = fpga_image_info_alloc(&ctx->pdev->dev);
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KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx->img_info);
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test->priv = ctx;
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return 0;
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}
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static void fpga_mgr_test_exit(struct kunit *test)
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{
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struct mgr_ctx *ctx = test->priv;
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fpga_image_info_free(ctx->img_info);
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platform_device_unregister(ctx->pdev);
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}
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static struct kunit_case fpga_mgr_test_cases[] = {
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KUNIT_CASE(fpga_mgr_test_get),
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KUNIT_CASE(fpga_mgr_test_lock),
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KUNIT_CASE(fpga_mgr_test_img_load_buf),
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KUNIT_CASE(fpga_mgr_test_img_load_sgt),
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{}
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};
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static struct kunit_suite fpga_mgr_suite = {
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.name = "fpga_mgr",
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.init = fpga_mgr_test_init,
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.exit = fpga_mgr_test_exit,
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.test_cases = fpga_mgr_test_cases,
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};
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kunit_test_suite(fpga_mgr_suite);
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MODULE_LICENSE("GPL");
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