forked from mirrors/linux
gpio: mlxbf3: Add gpio driver support
Add support for the BlueField-3 SoC GPIO driver. This driver configures and handles GPIO interrupts. It also enables a user to manipulate certain GPIO pins via libgpiod tools or other kernel drivers. The usables pins are defined via the "gpio-reserved-ranges" property. Signed-off-by: Asmaa Mnebhi <asmaa@nvidia.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
This commit is contained in:
Asmaa Mnebhi
Bartosz Golaszewski
parent
8efe124702
commit
cd33f216d2
3 changed files with 262 additions and 0 deletions
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@ -1599,6 +1599,19 @@ config GPIO_MLXBF2
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help
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Say Y here if you want GPIO support on Mellanox BlueField 2 SoC.
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config GPIO_MLXBF3
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tristate "Mellanox BlueField 3 SoC GPIO"
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depends on (MELLANOX_PLATFORM && ARM64) || COMPILE_TEST
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select GPIO_GENERIC
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select GPIOLIB_IRQCHIP
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help
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Say Y if you want GPIO support on Mellanox BlueField 3 SoC.
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This GPIO controller supports interrupt handling and enables the
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manipulation of certain GPIO pins.
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This controller should be used in parallel with pinctrl-mlxbf3 to
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control the desired GPIOs.
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This driver can also be built as a module called mlxbf3-gpio.
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config GPIO_ML_IOH
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tristate "OKI SEMICONDUCTOR ML7213 IOH GPIO support"
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depends on X86 || COMPILE_TEST
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@ -104,6 +104,7 @@ obj-$(CONFIG_GPIO_MERRIFIELD) += gpio-merrifield.o
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obj-$(CONFIG_GPIO_ML_IOH) += gpio-ml-ioh.o
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obj-$(CONFIG_GPIO_MLXBF) += gpio-mlxbf.o
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obj-$(CONFIG_GPIO_MLXBF2) += gpio-mlxbf2.o
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obj-$(CONFIG_GPIO_MLXBF3) += gpio-mlxbf3.o
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obj-$(CONFIG_GPIO_MM_LANTIQ) += gpio-mm-lantiq.o
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obj-$(CONFIG_GPIO_MOCKUP) += gpio-mockup.o
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obj-$(CONFIG_GPIO_MOXTET) += gpio-moxtet.o
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248
drivers/gpio/gpio-mlxbf3.c
Normal file
248
drivers/gpio/gpio-mlxbf3.c
Normal file
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@ -0,0 +1,248 @@
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// SPDX-License-Identifier: GPL-2.0-only or BSD-3-Clause
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/* Copyright (C) 2022 NVIDIA CORPORATION & AFFILIATES */
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#include <linux/bitfield.h>
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#include <linux/bitops.h>
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/gpio/driver.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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/*
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* There are 2 YU GPIO blocks:
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* gpio[0]: HOST_GPIO0->HOST_GPIO31
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* gpio[1]: HOST_GPIO32->HOST_GPIO55
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*/
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#define MLXBF3_GPIO_MAX_PINS_PER_BLOCK 32
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/*
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* fw_gpio[x] block registers and their offset
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*/
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#define MLXBF_GPIO_FW_OUTPUT_ENABLE_SET 0x00
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#define MLXBF_GPIO_FW_DATA_OUT_SET 0x04
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#define MLXBF_GPIO_FW_OUTPUT_ENABLE_CLEAR 0x00
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#define MLXBF_GPIO_FW_DATA_OUT_CLEAR 0x04
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#define MLXBF_GPIO_CAUSE_RISE_EN 0x00
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#define MLXBF_GPIO_CAUSE_FALL_EN 0x04
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#define MLXBF_GPIO_READ_DATA_IN 0x08
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#define MLXBF_GPIO_CAUSE_OR_CAUSE_EVTEN0 0x00
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#define MLXBF_GPIO_CAUSE_OR_EVTEN0 0x14
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#define MLXBF_GPIO_CAUSE_OR_CLRCAUSE 0x18
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struct mlxbf3_gpio_context {
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struct gpio_chip gc;
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/* YU GPIO block address */
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void __iomem *gpio_set_io;
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void __iomem *gpio_clr_io;
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void __iomem *gpio_io;
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/* YU GPIO cause block address */
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void __iomem *gpio_cause_io;
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};
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static void mlxbf3_gpio_irq_enable(struct irq_data *irqd)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
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struct mlxbf3_gpio_context *gs = gpiochip_get_data(gc);
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irq_hw_number_t offset = irqd_to_hwirq(irqd);
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unsigned long flags;
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u32 val;
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gpiochip_enable_irq(gc, offset);
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raw_spin_lock_irqsave(&gs->gc.bgpio_lock, flags);
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writel(BIT(offset), gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_CLRCAUSE);
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val = readl(gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0);
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val |= BIT(offset);
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writel(val, gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0);
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raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags);
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}
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static void mlxbf3_gpio_irq_disable(struct irq_data *irqd)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
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struct mlxbf3_gpio_context *gs = gpiochip_get_data(gc);
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irq_hw_number_t offset = irqd_to_hwirq(irqd);
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unsigned long flags;
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u32 val;
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raw_spin_lock_irqsave(&gs->gc.bgpio_lock, flags);
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val = readl(gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0);
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val &= ~BIT(offset);
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writel(val, gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0);
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raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags);
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gpiochip_disable_irq(gc, offset);
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}
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static irqreturn_t mlxbf3_gpio_irq_handler(int irq, void *ptr)
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{
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struct mlxbf3_gpio_context *gs = ptr;
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struct gpio_chip *gc = &gs->gc;
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unsigned long pending;
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u32 level;
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pending = readl(gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_CAUSE_EVTEN0);
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writel(pending, gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_CLRCAUSE);
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for_each_set_bit(level, &pending, gc->ngpio)
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generic_handle_domain_irq(gc->irq.domain, level);
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return IRQ_RETVAL(pending);
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}
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static int
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mlxbf3_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
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struct mlxbf3_gpio_context *gs = gpiochip_get_data(gc);
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irq_hw_number_t offset = irqd_to_hwirq(irqd);
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unsigned long flags;
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u32 val;
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raw_spin_lock_irqsave(&gs->gc.bgpio_lock, flags);
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switch (type & IRQ_TYPE_SENSE_MASK) {
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case IRQ_TYPE_EDGE_BOTH:
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val = readl(gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN);
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val |= BIT(offset);
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writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN);
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val = readl(gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN);
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val |= BIT(offset);
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writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN);
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break;
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case IRQ_TYPE_EDGE_RISING:
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val = readl(gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN);
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val |= BIT(offset);
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writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN);
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break;
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case IRQ_TYPE_EDGE_FALLING:
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val = readl(gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN);
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val |= BIT(offset);
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writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN);
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break;
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default:
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raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags);
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return -EINVAL;
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}
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raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags);
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irq_set_handler_locked(irqd, handle_edge_irq);
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return 0;
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}
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/* This function needs to be defined for handle_edge_irq() */
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static void mlxbf3_gpio_irq_ack(struct irq_data *data)
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{
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}
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static const struct irq_chip gpio_mlxbf3_irqchip = {
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.name = "MLNXBF33",
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.irq_ack = mlxbf3_gpio_irq_ack,
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.irq_set_type = mlxbf3_gpio_irq_set_type,
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.irq_enable = mlxbf3_gpio_irq_enable,
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.irq_disable = mlxbf3_gpio_irq_disable,
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.flags = IRQCHIP_IMMUTABLE,
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GPIOCHIP_IRQ_RESOURCE_HELPERS,
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};
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static int mlxbf3_gpio_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct mlxbf3_gpio_context *gs;
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struct gpio_irq_chip *girq;
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struct gpio_chip *gc;
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int ret, irq;
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gs = devm_kzalloc(dev, sizeof(*gs), GFP_KERNEL);
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if (!gs)
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return -ENOMEM;
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gs->gpio_io = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(gs->gpio_io))
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return PTR_ERR(gs->gpio_io);
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gs->gpio_cause_io = devm_platform_ioremap_resource(pdev, 1);
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if (IS_ERR(gs->gpio_cause_io))
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return PTR_ERR(gs->gpio_cause_io);
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gs->gpio_set_io = devm_platform_ioremap_resource(pdev, 2);
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if (IS_ERR(gs->gpio_set_io))
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return PTR_ERR(gs->gpio_set_io);
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gs->gpio_clr_io = devm_platform_ioremap_resource(pdev, 3);
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if (IS_ERR(gs->gpio_clr_io))
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return PTR_ERR(gs->gpio_clr_io);
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gc = &gs->gc;
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ret = bgpio_init(gc, dev, 4,
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gs->gpio_io + MLXBF_GPIO_READ_DATA_IN,
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gs->gpio_set_io + MLXBF_GPIO_FW_DATA_OUT_SET,
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gs->gpio_clr_io + MLXBF_GPIO_FW_DATA_OUT_CLEAR,
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gs->gpio_set_io + MLXBF_GPIO_FW_OUTPUT_ENABLE_SET,
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gs->gpio_clr_io + MLXBF_GPIO_FW_OUTPUT_ENABLE_CLEAR, 0);
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gc->request = gpiochip_generic_request;
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gc->free = gpiochip_generic_free;
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gc->owner = THIS_MODULE;
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irq = platform_get_irq(pdev, 0);
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if (irq >= 0) {
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girq = &gs->gc.irq;
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gpio_irq_chip_set_chip(girq, &gpio_mlxbf3_irqchip);
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girq->default_type = IRQ_TYPE_NONE;
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/* This will let us handle the parent IRQ in the driver */
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girq->num_parents = 0;
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girq->parents = NULL;
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girq->parent_handler = NULL;
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girq->handler = handle_bad_irq;
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/*
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* Directly request the irq here instead of passing
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* a flow-handler because the irq is shared.
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*/
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ret = devm_request_irq(dev, irq, mlxbf3_gpio_irq_handler,
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IRQF_SHARED, dev_name(dev), gs);
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if (ret)
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return dev_err_probe(dev, ret, "failed to request IRQ");
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}
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platform_set_drvdata(pdev, gs);
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ret = devm_gpiochip_add_data(dev, &gs->gc, gs);
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if (ret)
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dev_err_probe(dev, ret, "Failed adding memory mapped gpiochip\n");
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return 0;
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}
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static const struct acpi_device_id mlxbf3_gpio_acpi_match[] = {
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{ "MLNXBF33", 0 },
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{}
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};
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MODULE_DEVICE_TABLE(acpi, mlxbf3_gpio_acpi_match);
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static struct platform_driver mlxbf3_gpio_driver = {
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.driver = {
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.name = "mlxbf3_gpio",
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.acpi_match_table = mlxbf3_gpio_acpi_match,
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},
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.probe = mlxbf3_gpio_probe,
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};
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module_platform_driver(mlxbf3_gpio_driver);
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MODULE_DESCRIPTION("NVIDIA BlueField-3 GPIO Driver");
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MODULE_AUTHOR("Asmaa Mnebhi <asmaa@nvidia.com>");
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MODULE_LICENSE("Dual BSD/GPL");
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