forked from mirrors/linux
dmaengine: dma40: Add support to split up large elements
The maximum transfer size of the stedma40 is (64k-1) x data-width. If the transfer size of one element exceeds this limit the job is split up and sent as linked transfer. Signed-off-by: Per Forlin <per.forlin@linaro.org> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
This commit is contained in:
Per Forlin
Dan Williams
parent
e8a7e48bb2
commit
d49278e335
4 changed files with 351 additions and 130 deletions
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@ -13,6 +13,14 @@
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#include <linux/workqueue.h>
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#include <linux/interrupt.h>
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/*
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* Maxium size for a single dma descriptor
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* Size is limited to 16 bits.
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* Size is in the units of addr-widths (1,2,4,8 bytes)
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* Larger transfers will be split up to multiple linked desc
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*/
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#define STEDMA40_MAX_SEG_SIZE 0xFFFF
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/* dev types for memcpy */
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#define STEDMA40_DEV_DST_MEMORY (-1)
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#define STEDMA40_DEV_SRC_MEMORY (-1)
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@ -1,5 +1,6 @@
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/*
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* Copyright (C) ST-Ericsson SA 2007-2010
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* Copyright (C) Ericsson AB 2007-2008
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* Copyright (C) ST-Ericsson SA 2008-2010
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* Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
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* Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
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* License terms: GNU General Public License (GPL) version 2
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@ -554,8 +555,66 @@ static struct d40_desc *d40_last_queued(struct d40_chan *d40c)
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return d;
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}
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/* Support functions for logical channels */
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static int d40_psize_2_burst_size(bool is_log, int psize)
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{
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if (is_log) {
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if (psize == STEDMA40_PSIZE_LOG_1)
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return 1;
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} else {
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if (psize == STEDMA40_PSIZE_PHY_1)
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return 1;
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}
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return 2 << psize;
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}
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/*
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* The dma only supports transmitting packages up to
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* STEDMA40_MAX_SEG_SIZE << data_width. Calculate the total number of
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* dma elements required to send the entire sg list
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*/
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static int d40_size_2_dmalen(int size, u32 data_width1, u32 data_width2)
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{
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int dmalen;
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u32 max_w = max(data_width1, data_width2);
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u32 min_w = min(data_width1, data_width2);
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u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE << min_w, 1 << max_w);
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if (seg_max > STEDMA40_MAX_SEG_SIZE)
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seg_max -= (1 << max_w);
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if (!IS_ALIGNED(size, 1 << max_w))
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return -EINVAL;
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if (size <= seg_max)
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dmalen = 1;
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else {
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dmalen = size / seg_max;
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if (dmalen * seg_max < size)
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dmalen++;
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}
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return dmalen;
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}
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static int d40_sg_2_dmalen(struct scatterlist *sgl, int sg_len,
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u32 data_width1, u32 data_width2)
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{
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struct scatterlist *sg;
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int i;
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int len = 0;
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int ret;
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for_each_sg(sgl, sg, sg_len, i) {
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ret = d40_size_2_dmalen(sg_dma_len(sg),
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data_width1, data_width2);
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if (ret < 0)
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return ret;
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len += ret;
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}
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return len;
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}
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/* Support functions for logical channels */
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static int d40_channel_execute_command(struct d40_chan *d40c,
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enum d40_command command)
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@ -1241,6 +1300,21 @@ static int d40_validate_conf(struct d40_chan *d40c,
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res = -EINVAL;
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}
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if (d40_psize_2_burst_size(is_log, conf->src_info.psize) *
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(1 << conf->src_info.data_width) !=
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d40_psize_2_burst_size(is_log, conf->dst_info.psize) *
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(1 << conf->dst_info.data_width)) {
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/*
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* The DMAC hardware only supports
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* src (burst x width) == dst (burst x width)
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*/
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dev_err(&d40c->chan.dev->device,
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"[%s] src (burst x width) != dst (burst x width)\n",
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__func__);
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res = -EINVAL;
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}
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return res;
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}
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@ -1638,13 +1712,21 @@ struct dma_async_tx_descriptor *stedma40_memcpy_sg(struct dma_chan *chan,
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if (d40d == NULL)
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goto err;
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d40d->lli_len = sgl_len;
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d40d->lli_len = d40_sg_2_dmalen(sgl_dst, sgl_len,
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d40c->dma_cfg.src_info.data_width,
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d40c->dma_cfg.dst_info.data_width);
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if (d40d->lli_len < 0) {
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dev_err(&d40c->chan.dev->device,
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"[%s] Unaligned size\n", __func__);
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goto err;
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}
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d40d->lli_current = 0;
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d40d->txd.flags = dma_flags;
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if (d40c->log_num != D40_PHY_CHAN) {
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if (d40_pool_lli_alloc(d40d, sgl_len, true) < 0) {
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if (d40_pool_lli_alloc(d40d, d40d->lli_len, true) < 0) {
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dev_err(&d40c->chan.dev->device,
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"[%s] Out of memory\n", __func__);
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goto err;
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@ -1654,15 +1736,17 @@ struct dma_async_tx_descriptor *stedma40_memcpy_sg(struct dma_chan *chan,
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sgl_len,
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d40d->lli_log.src,
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d40c->log_def.lcsp1,
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d40c->dma_cfg.src_info.data_width);
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d40c->dma_cfg.src_info.data_width,
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d40c->dma_cfg.dst_info.data_width);
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(void) d40_log_sg_to_lli(sgl_dst,
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sgl_len,
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d40d->lli_log.dst,
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d40c->log_def.lcsp3,
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d40c->dma_cfg.dst_info.data_width);
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d40c->dma_cfg.dst_info.data_width,
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d40c->dma_cfg.src_info.data_width);
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} else {
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if (d40_pool_lli_alloc(d40d, sgl_len, false) < 0) {
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if (d40_pool_lli_alloc(d40d, d40d->lli_len, false) < 0) {
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dev_err(&d40c->chan.dev->device,
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"[%s] Out of memory\n", __func__);
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goto err;
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@ -1675,6 +1759,7 @@ struct dma_async_tx_descriptor *stedma40_memcpy_sg(struct dma_chan *chan,
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virt_to_phys(d40d->lli_phy.src),
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d40c->src_def_cfg,
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d40c->dma_cfg.src_info.data_width,
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d40c->dma_cfg.dst_info.data_width,
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d40c->dma_cfg.src_info.psize);
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if (res < 0)
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@ -1687,6 +1772,7 @@ struct dma_async_tx_descriptor *stedma40_memcpy_sg(struct dma_chan *chan,
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virt_to_phys(d40d->lli_phy.dst),
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d40c->dst_def_cfg,
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d40c->dma_cfg.dst_info.data_width,
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d40c->dma_cfg.src_info.data_width,
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d40c->dma_cfg.dst_info.psize);
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if (res < 0)
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@ -1826,7 +1912,6 @@ static struct dma_async_tx_descriptor *d40_prep_memcpy(struct dma_chan *chan,
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struct d40_chan *d40c = container_of(chan, struct d40_chan,
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chan);
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unsigned long flags;
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int err = 0;
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if (d40c->phy_chan == NULL) {
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dev_err(&d40c->chan.dev->device,
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@ -1844,6 +1929,15 @@ static struct dma_async_tx_descriptor *d40_prep_memcpy(struct dma_chan *chan,
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}
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d40d->txd.flags = dma_flags;
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d40d->lli_len = d40_size_2_dmalen(size,
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d40c->dma_cfg.src_info.data_width,
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d40c->dma_cfg.dst_info.data_width);
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if (d40d->lli_len < 0) {
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dev_err(&d40c->chan.dev->device,
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"[%s] Unaligned size\n", __func__);
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goto err;
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}
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dma_async_tx_descriptor_init(&d40d->txd, chan);
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@ -1851,37 +1945,40 @@ static struct dma_async_tx_descriptor *d40_prep_memcpy(struct dma_chan *chan,
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if (d40c->log_num != D40_PHY_CHAN) {
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if (d40_pool_lli_alloc(d40d, 1, true) < 0) {
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if (d40_pool_lli_alloc(d40d, d40d->lli_len, true) < 0) {
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dev_err(&d40c->chan.dev->device,
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"[%s] Out of memory\n", __func__);
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goto err;
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}
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d40d->lli_len = 1;
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d40d->lli_current = 0;
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d40_log_fill_lli(d40d->lli_log.src,
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src,
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size,
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d40c->log_def.lcsp1,
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d40c->dma_cfg.src_info.data_width,
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true);
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if (d40_log_buf_to_lli(d40d->lli_log.src,
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src,
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size,
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d40c->log_def.lcsp1,
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d40c->dma_cfg.src_info.data_width,
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d40c->dma_cfg.dst_info.data_width,
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true) == NULL)
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goto err;
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d40_log_fill_lli(d40d->lli_log.dst,
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dst,
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size,
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d40c->log_def.lcsp3,
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d40c->dma_cfg.dst_info.data_width,
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true);
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if (d40_log_buf_to_lli(d40d->lli_log.dst,
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dst,
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size,
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d40c->log_def.lcsp3,
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d40c->dma_cfg.dst_info.data_width,
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d40c->dma_cfg.src_info.data_width,
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true) == NULL)
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goto err;
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} else {
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if (d40_pool_lli_alloc(d40d, 1, false) < 0) {
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if (d40_pool_lli_alloc(d40d, d40d->lli_len, false) < 0) {
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dev_err(&d40c->chan.dev->device,
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"[%s] Out of memory\n", __func__);
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goto err;
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}
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err = d40_phy_fill_lli(d40d->lli_phy.src,
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if (d40_phy_buf_to_lli(d40d->lli_phy.src,
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src,
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size,
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d40c->dma_cfg.src_info.psize,
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@ -1889,11 +1986,11 @@ static struct dma_async_tx_descriptor *d40_prep_memcpy(struct dma_chan *chan,
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d40c->src_def_cfg,
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true,
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d40c->dma_cfg.src_info.data_width,
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false);
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if (err)
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goto err_fill_lli;
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d40c->dma_cfg.dst_info.data_width,
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false) == NULL)
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goto err;
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err = d40_phy_fill_lli(d40d->lli_phy.dst,
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if (d40_phy_buf_to_lli(d40d->lli_phy.dst,
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dst,
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size,
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d40c->dma_cfg.dst_info.psize,
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@ -1901,10 +1998,9 @@ static struct dma_async_tx_descriptor *d40_prep_memcpy(struct dma_chan *chan,
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d40c->dst_def_cfg,
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true,
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d40c->dma_cfg.dst_info.data_width,
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false);
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if (err)
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goto err_fill_lli;
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d40c->dma_cfg.src_info.data_width,
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false) == NULL)
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goto err;
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(void) dma_map_single(d40c->base->dev, d40d->lli_phy.src,
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d40d->lli_pool.size, DMA_TO_DEVICE);
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@ -1913,9 +2009,6 @@ static struct dma_async_tx_descriptor *d40_prep_memcpy(struct dma_chan *chan,
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spin_unlock_irqrestore(&d40c->lock, flags);
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return &d40d->txd;
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err_fill_lli:
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dev_err(&d40c->chan.dev->device,
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"[%s] Failed filling in PHY LLI\n", __func__);
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err:
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if (d40d)
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d40_desc_free(d40c, d40d);
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@ -1945,13 +2038,21 @@ static int d40_prep_slave_sg_log(struct d40_desc *d40d,
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dma_addr_t dev_addr = 0;
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int total_size;
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if (d40_pool_lli_alloc(d40d, sg_len, true) < 0) {
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d40d->lli_len = d40_sg_2_dmalen(sgl, sg_len,
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d40c->dma_cfg.src_info.data_width,
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d40c->dma_cfg.dst_info.data_width);
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if (d40d->lli_len < 0) {
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dev_err(&d40c->chan.dev->device,
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"[%s] Unaligned size\n", __func__);
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return -EINVAL;
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}
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if (d40_pool_lli_alloc(d40d, d40d->lli_len, true) < 0) {
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dev_err(&d40c->chan.dev->device,
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"[%s] Out of memory\n", __func__);
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return -ENOMEM;
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}
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d40d->lli_len = sg_len;
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d40d->lli_current = 0;
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if (direction == DMA_FROM_DEVICE)
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@ -1993,13 +2094,21 @@ static int d40_prep_slave_sg_phy(struct d40_desc *d40d,
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dma_addr_t dst_dev_addr;
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int res;
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if (d40_pool_lli_alloc(d40d, sgl_len, false) < 0) {
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d40d->lli_len = d40_sg_2_dmalen(sgl, sgl_len,
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d40c->dma_cfg.src_info.data_width,
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d40c->dma_cfg.dst_info.data_width);
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if (d40d->lli_len < 0) {
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dev_err(&d40c->chan.dev->device,
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"[%s] Unaligned size\n", __func__);
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return -EINVAL;
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}
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if (d40_pool_lli_alloc(d40d, d40d->lli_len, false) < 0) {
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dev_err(&d40c->chan.dev->device,
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"[%s] Out of memory\n", __func__);
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return -ENOMEM;
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}
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d40d->lli_len = sgl_len;
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d40d->lli_current = 0;
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if (direction == DMA_FROM_DEVICE) {
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@ -2024,6 +2133,7 @@ static int d40_prep_slave_sg_phy(struct d40_desc *d40d,
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virt_to_phys(d40d->lli_phy.src),
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d40c->src_def_cfg,
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d40c->dma_cfg.src_info.data_width,
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d40c->dma_cfg.dst_info.data_width,
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d40c->dma_cfg.src_info.psize);
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if (res < 0)
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return res;
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@ -2035,6 +2145,7 @@ static int d40_prep_slave_sg_phy(struct d40_desc *d40d,
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virt_to_phys(d40d->lli_phy.dst),
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d40c->dst_def_cfg,
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d40c->dma_cfg.dst_info.data_width,
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d40c->dma_cfg.src_info.data_width,
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d40c->dma_cfg.dst_info.psize);
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if (res < 0)
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return res;
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@ -2244,6 +2355,8 @@ static void d40_set_runtime_config(struct dma_chan *chan,
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psize = STEDMA40_PSIZE_PHY_8;
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else if (config_maxburst >= 4)
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psize = STEDMA40_PSIZE_PHY_4;
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else if (config_maxburst >= 2)
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psize = STEDMA40_PSIZE_PHY_2;
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else
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psize = STEDMA40_PSIZE_PHY_1;
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}
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@ -1,6 +1,6 @@
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/*
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* Copyright (C) ST-Ericsson SA 2007-2010
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* Author: Per Friden <per.friden@stericsson.com> for ST-Ericsson
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* Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
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* Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
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* License terms: GNU General Public License (GPL) version 2
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*/
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@ -122,15 +122,15 @@ void d40_phy_cfg(struct stedma40_chan_cfg *cfg,
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*dst_cfg = dst;
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}
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int d40_phy_fill_lli(struct d40_phy_lli *lli,
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dma_addr_t data,
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u32 data_size,
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int psize,
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dma_addr_t next_lli,
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u32 reg_cfg,
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bool term_int,
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u32 data_width,
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bool is_device)
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static int d40_phy_fill_lli(struct d40_phy_lli *lli,
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dma_addr_t data,
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u32 data_size,
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int psize,
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dma_addr_t next_lli,
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u32 reg_cfg,
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bool term_int,
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u32 data_width,
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bool is_device)
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{
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int num_elems;
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@ -139,13 +139,6 @@ int d40_phy_fill_lli(struct d40_phy_lli *lli,
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else
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num_elems = 2 << psize;
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/*
|
||||
* Size is 16bit. data_width is 8, 16, 32 or 64 bit
|
||||
* Block large than 64 KiB must be split.
|
||||
*/
|
||||
if (data_size > (0xffff << data_width))
|
||||
return -EINVAL;
|
||||
|
||||
/* Must be aligned */
|
||||
if (!IS_ALIGNED(data, 0x1 << data_width))
|
||||
return -EINVAL;
|
||||
|
|
@ -187,55 +180,118 @@ int d40_phy_fill_lli(struct d40_phy_lli *lli,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int d40_seg_size(int size, int data_width1, int data_width2)
|
||||
{
|
||||
u32 max_w = max(data_width1, data_width2);
|
||||
u32 min_w = min(data_width1, data_width2);
|
||||
u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE << min_w, 1 << max_w);
|
||||
|
||||
if (seg_max > STEDMA40_MAX_SEG_SIZE)
|
||||
seg_max -= (1 << max_w);
|
||||
|
||||
if (size <= seg_max)
|
||||
return size;
|
||||
|
||||
if (size <= 2 * seg_max)
|
||||
return ALIGN(size / 2, 1 << max_w);
|
||||
|
||||
return seg_max;
|
||||
}
|
||||
|
||||
struct d40_phy_lli *d40_phy_buf_to_lli(struct d40_phy_lli *lli,
|
||||
dma_addr_t addr,
|
||||
u32 size,
|
||||
int psize,
|
||||
dma_addr_t lli_phys,
|
||||
u32 reg_cfg,
|
||||
bool term_int,
|
||||
u32 data_width1,
|
||||
u32 data_width2,
|
||||
bool is_device)
|
||||
{
|
||||
int err;
|
||||
dma_addr_t next = lli_phys;
|
||||
int size_rest = size;
|
||||
int size_seg = 0;
|
||||
|
||||
do {
|
||||
size_seg = d40_seg_size(size_rest, data_width1, data_width2);
|
||||
size_rest -= size_seg;
|
||||
|
||||
if (term_int && size_rest == 0)
|
||||
next = 0;
|
||||
else
|
||||
next = ALIGN(next + sizeof(struct d40_phy_lli),
|
||||
D40_LLI_ALIGN);
|
||||
|
||||
err = d40_phy_fill_lli(lli,
|
||||
addr,
|
||||
size_seg,
|
||||
psize,
|
||||
next,
|
||||
reg_cfg,
|
||||
!next,
|
||||
data_width1,
|
||||
is_device);
|
||||
|
||||
if (err)
|
||||
goto err;
|
||||
|
||||
lli++;
|
||||
if (!is_device)
|
||||
addr += size_seg;
|
||||
} while (size_rest);
|
||||
|
||||
return lli;
|
||||
|
||||
err:
|
||||
return NULL;
|
||||
}
|
||||
|
||||
int d40_phy_sg_to_lli(struct scatterlist *sg,
|
||||
int sg_len,
|
||||
dma_addr_t target,
|
||||
struct d40_phy_lli *lli,
|
||||
struct d40_phy_lli *lli_sg,
|
||||
dma_addr_t lli_phys,
|
||||
u32 reg_cfg,
|
||||
u32 data_width,
|
||||
u32 data_width1,
|
||||
u32 data_width2,
|
||||
int psize)
|
||||
{
|
||||
int total_size = 0;
|
||||
int i;
|
||||
struct scatterlist *current_sg = sg;
|
||||
dma_addr_t next_lli_phys;
|
||||
dma_addr_t dst;
|
||||
int err = 0;
|
||||
struct d40_phy_lli *lli = lli_sg;
|
||||
dma_addr_t l_phys = lli_phys;
|
||||
|
||||
for_each_sg(sg, current_sg, sg_len, i) {
|
||||
|
||||
total_size += sg_dma_len(current_sg);
|
||||
|
||||
/* If this scatter list entry is the last one, no next link */
|
||||
if (sg_len - 1 == i)
|
||||
next_lli_phys = 0;
|
||||
else
|
||||
next_lli_phys = ALIGN(lli_phys + (i + 1) *
|
||||
sizeof(struct d40_phy_lli),
|
||||
D40_LLI_ALIGN);
|
||||
|
||||
if (target)
|
||||
dst = target;
|
||||
else
|
||||
dst = sg_phys(current_sg);
|
||||
|
||||
err = d40_phy_fill_lli(&lli[i],
|
||||
dst,
|
||||
sg_dma_len(current_sg),
|
||||
psize,
|
||||
next_lli_phys,
|
||||
reg_cfg,
|
||||
!next_lli_phys,
|
||||
data_width,
|
||||
target == dst);
|
||||
if (err)
|
||||
goto err;
|
||||
l_phys = ALIGN(lli_phys + (lli - lli_sg) *
|
||||
sizeof(struct d40_phy_lli), D40_LLI_ALIGN);
|
||||
|
||||
lli = d40_phy_buf_to_lli(lli,
|
||||
dst,
|
||||
sg_dma_len(current_sg),
|
||||
psize,
|
||||
l_phys,
|
||||
reg_cfg,
|
||||
sg_len - 1 == i,
|
||||
data_width1,
|
||||
data_width2,
|
||||
target == dst);
|
||||
if (lli == NULL)
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return total_size;
|
||||
err:
|
||||
return err;
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -315,17 +371,20 @@ void d40_log_lli_lcla_write(struct d40_log_lli *lcla,
|
|||
writel(lli_dst->lcsp13, &lcla[1].lcsp13);
|
||||
}
|
||||
|
||||
void d40_log_fill_lli(struct d40_log_lli *lli,
|
||||
dma_addr_t data, u32 data_size,
|
||||
u32 reg_cfg,
|
||||
u32 data_width,
|
||||
bool addr_inc)
|
||||
static void d40_log_fill_lli(struct d40_log_lli *lli,
|
||||
dma_addr_t data, u32 data_size,
|
||||
u32 reg_cfg,
|
||||
u32 data_width,
|
||||
bool addr_inc)
|
||||
{
|
||||
lli->lcsp13 = reg_cfg;
|
||||
|
||||
/* The number of elements to transfer */
|
||||
lli->lcsp02 = ((data_size >> data_width) <<
|
||||
D40_MEM_LCSP0_ECNT_POS) & D40_MEM_LCSP0_ECNT_MASK;
|
||||
|
||||
BUG_ON((data_size >> data_width) > STEDMA40_MAX_SEG_SIZE);
|
||||
|
||||
/* 16 LSBs address of the current element */
|
||||
lli->lcsp02 |= data & D40_MEM_LCSP0_SPTR_MASK;
|
||||
/* 16 MSBs address of the current element */
|
||||
|
|
@ -348,55 +407,94 @@ int d40_log_sg_to_dev(struct scatterlist *sg,
|
|||
int total_size = 0;
|
||||
struct scatterlist *current_sg = sg;
|
||||
int i;
|
||||
struct d40_log_lli *lli_src = lli->src;
|
||||
struct d40_log_lli *lli_dst = lli->dst;
|
||||
|
||||
for_each_sg(sg, current_sg, sg_len, i) {
|
||||
total_size += sg_dma_len(current_sg);
|
||||
|
||||
if (direction == DMA_TO_DEVICE) {
|
||||
d40_log_fill_lli(&lli->src[i],
|
||||
sg_phys(current_sg),
|
||||
sg_dma_len(current_sg),
|
||||
lcsp->lcsp1, src_data_width,
|
||||
true);
|
||||
d40_log_fill_lli(&lli->dst[i],
|
||||
dev_addr,
|
||||
sg_dma_len(current_sg),
|
||||
lcsp->lcsp3, dst_data_width,
|
||||
false);
|
||||
lli_src =
|
||||
d40_log_buf_to_lli(lli_src,
|
||||
sg_phys(current_sg),
|
||||
sg_dma_len(current_sg),
|
||||
lcsp->lcsp1, src_data_width,
|
||||
dst_data_width,
|
||||
true);
|
||||
lli_dst =
|
||||
d40_log_buf_to_lli(lli_dst,
|
||||
dev_addr,
|
||||
sg_dma_len(current_sg),
|
||||
lcsp->lcsp3, dst_data_width,
|
||||
src_data_width,
|
||||
false);
|
||||
} else {
|
||||
d40_log_fill_lli(&lli->dst[i],
|
||||
sg_phys(current_sg),
|
||||
sg_dma_len(current_sg),
|
||||
lcsp->lcsp3, dst_data_width,
|
||||
true);
|
||||
d40_log_fill_lli(&lli->src[i],
|
||||
dev_addr,
|
||||
sg_dma_len(current_sg),
|
||||
lcsp->lcsp1, src_data_width,
|
||||
false);
|
||||
lli_dst =
|
||||
d40_log_buf_to_lli(lli_dst,
|
||||
sg_phys(current_sg),
|
||||
sg_dma_len(current_sg),
|
||||
lcsp->lcsp3, dst_data_width,
|
||||
src_data_width,
|
||||
true);
|
||||
lli_src =
|
||||
d40_log_buf_to_lli(lli_src,
|
||||
dev_addr,
|
||||
sg_dma_len(current_sg),
|
||||
lcsp->lcsp1, src_data_width,
|
||||
dst_data_width,
|
||||
false);
|
||||
}
|
||||
}
|
||||
return total_size;
|
||||
}
|
||||
|
||||
struct d40_log_lli *d40_log_buf_to_lli(struct d40_log_lli *lli_sg,
|
||||
dma_addr_t addr,
|
||||
int size,
|
||||
u32 lcsp13, /* src or dst*/
|
||||
u32 data_width1,
|
||||
u32 data_width2,
|
||||
bool addr_inc)
|
||||
{
|
||||
struct d40_log_lli *lli = lli_sg;
|
||||
int size_rest = size;
|
||||
int size_seg = 0;
|
||||
|
||||
do {
|
||||
size_seg = d40_seg_size(size_rest, data_width1, data_width2);
|
||||
size_rest -= size_seg;
|
||||
|
||||
d40_log_fill_lli(lli,
|
||||
addr,
|
||||
size_seg,
|
||||
lcsp13, data_width1,
|
||||
addr_inc);
|
||||
if (addr_inc)
|
||||
addr += size_seg;
|
||||
lli++;
|
||||
} while (size_rest);
|
||||
|
||||
return lli;
|
||||
}
|
||||
|
||||
int d40_log_sg_to_lli(struct scatterlist *sg,
|
||||
int sg_len,
|
||||
struct d40_log_lli *lli_sg,
|
||||
u32 lcsp13, /* src or dst*/
|
||||
u32 data_width)
|
||||
u32 data_width1, u32 data_width2)
|
||||
{
|
||||
int total_size = 0;
|
||||
struct scatterlist *current_sg = sg;
|
||||
int i;
|
||||
struct d40_log_lli *lli = lli_sg;
|
||||
|
||||
for_each_sg(sg, current_sg, sg_len, i) {
|
||||
total_size += sg_dma_len(current_sg);
|
||||
|
||||
d40_log_fill_lli(&lli_sg[i],
|
||||
sg_phys(current_sg),
|
||||
sg_dma_len(current_sg),
|
||||
lcsp13, data_width,
|
||||
true);
|
||||
lli = d40_log_buf_to_lli(lli,
|
||||
sg_phys(current_sg),
|
||||
sg_dma_len(current_sg),
|
||||
lcsp13,
|
||||
data_width1, data_width2, true);
|
||||
}
|
||||
return total_size;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -292,18 +292,20 @@ int d40_phy_sg_to_lli(struct scatterlist *sg,
|
|||
struct d40_phy_lli *lli,
|
||||
dma_addr_t lli_phys,
|
||||
u32 reg_cfg,
|
||||
u32 data_width,
|
||||
u32 data_width1,
|
||||
u32 data_width2,
|
||||
int psize);
|
||||
|
||||
int d40_phy_fill_lli(struct d40_phy_lli *lli,
|
||||
dma_addr_t data,
|
||||
u32 data_size,
|
||||
int psize,
|
||||
dma_addr_t next_lli,
|
||||
u32 reg_cfg,
|
||||
bool term_int,
|
||||
u32 data_width,
|
||||
bool is_device);
|
||||
struct d40_phy_lli *d40_phy_buf_to_lli(struct d40_phy_lli *lli,
|
||||
dma_addr_t data,
|
||||
u32 data_size,
|
||||
int psize,
|
||||
dma_addr_t next_lli,
|
||||
u32 reg_cfg,
|
||||
bool term_int,
|
||||
u32 data_width1,
|
||||
u32 data_width2,
|
||||
bool is_device);
|
||||
|
||||
void d40_phy_lli_write(void __iomem *virtbase,
|
||||
u32 phy_chan_num,
|
||||
|
|
@ -312,12 +314,12 @@ void d40_phy_lli_write(void __iomem *virtbase,
|
|||
|
||||
/* Logical channels */
|
||||
|
||||
void d40_log_fill_lli(struct d40_log_lli *lli,
|
||||
dma_addr_t data,
|
||||
u32 data_size,
|
||||
u32 reg_cfg,
|
||||
u32 data_width,
|
||||
bool addr_inc);
|
||||
struct d40_log_lli *d40_log_buf_to_lli(struct d40_log_lli *lli_sg,
|
||||
dma_addr_t addr,
|
||||
int size,
|
||||
u32 lcsp13, /* src or dst*/
|
||||
u32 data_width1, u32 data_width2,
|
||||
bool addr_inc);
|
||||
|
||||
int d40_log_sg_to_dev(struct scatterlist *sg,
|
||||
int sg_len,
|
||||
|
|
@ -332,7 +334,7 @@ int d40_log_sg_to_lli(struct scatterlist *sg,
|
|||
int sg_len,
|
||||
struct d40_log_lli *lli_sg,
|
||||
u32 lcsp13, /* src or dst*/
|
||||
u32 data_width);
|
||||
u32 data_width1, u32 data_width2);
|
||||
|
||||
void d40_log_lli_lcpa_write(struct d40_log_lli_full *lcpa,
|
||||
struct d40_log_lli *lli_dst,
|
||||
|
|
|
|||
Loading…
Reference in a new issue