forked from mirrors/linux
		
	PCI/PM: Increase wait time after resume
PCIe r6.0 sec 6.6.1 prescribes that a device must be able to respond to config requests within 1.0 s (PCI_RESET_WAIT) after exiting conventional reset and this same delay is prescribed when coming out of D3cold (as that involves reset too). A device that requires more than 1 second to initialize after reset may respond to config requests with Request Retry Status completions (sec 2.3.1), and we accommodate that in Linux with a 60 second cap (PCIE_RESET_READY_POLL_MS). Previously we waited up to PCIE_RESET_READY_POLL_MS only in the reset code path, not in the resume path. However, a device has surfaced, namely Intel Titan Ridge xHCI, which requires a longer delay also in the resume code path. Make the resume code path to use this same extended delay as the reset path. Link: https://bugzilla.kernel.org/show_bug.cgi?id=216728 Link: https://lore.kernel.org/r/20230404052714.51315-2-mika.westerberg@linux.intel.com Reported-by: Chris Chiu <chris.chiu@canonical.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Lukas Wunner <lukas@wunner.de>
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					@ -572,7 +572,8 @@ static void pci_pm_default_resume_early(struct pci_dev *pci_dev)
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static void pci_pm_bridge_power_up_actions(struct pci_dev *pci_dev)
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					static void pci_pm_bridge_power_up_actions(struct pci_dev *pci_dev)
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{
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					{
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	pci_bridge_wait_for_secondary_bus(pci_dev, "resume", PCI_RESET_WAIT);
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						pci_bridge_wait_for_secondary_bus(pci_dev, "resume",
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										  PCIE_RESET_READY_POLL_MS);
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	/*
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						/*
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	 * When powering on a bridge from D3cold, the whole hierarchy may be
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						 * When powering on a bridge from D3cold, the whole hierarchy may be
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	 * powered on into D0uninitialized state, resume them to give them a
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						 * powered on into D0uninitialized state, resume them to give them a
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