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x86/xen: don't write ptes directly in 32-bit PV guests

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In some cases 32-bit PAE PV guests still write PTEs directly instead of
using hypercalls. This is especially bad when clearing a PTE as this is
done via 32-bit writes which will produce intermediate L1TF attackable
PTEs.

Change the code to use hypercalls instead.

Signed-off-by: Juergen Gross <jgross@suse.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
This commit is contained in:
Juergen Gross 2018-08-21 17:37:54 +02:00 committed by Boris Ostrovsky
parent 75f2d3a0ce
commit f7c90c2aa4
1 changed files with 3 additions and 4 deletions
repo.diff.show_diff_stats Download patch file Download diff file Expand all files Collapse all files

7
arch/x86/xen/mmu_pv.c
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@ -434,14 +434,13 @@ static void xen_set_pud(pud_t *ptr, pud_t val)
static void xen_set_pte_atomic(pte_t *ptep, pte_t pte) static void xen_set_pte_atomic(pte_t *ptep, pte_t pte)
{ {
trace_xen_mmu_set_pte_atomic(ptep, pte); trace_xen_mmu_set_pte_atomic(ptep, pte);
set_64bit((u64 *)ptep, native_pte_val(pte)); __xen_set_pte(ptep, pte);
} }
static void xen_pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) static void xen_pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
{ {
trace_xen_mmu_pte_clear(mm, addr, ptep); trace_xen_mmu_pte_clear(mm, addr, ptep);
if (!xen_batched_set_pte(ptep, native_make_pte(0))) __xen_set_pte(ptep, native_make_pte(0));
native_pte_clear(mm, addr, ptep);
} }
static void xen_pmd_clear(pmd_t *pmdp) static void xen_pmd_clear(pmd_t *pmdp)
@ -1569,7 +1568,7 @@ static void __init xen_set_pte_init(pte_t *ptep, pte_t pte)
pte = __pte_ma(((pte_val_ma(*ptep) & _PAGE_RW) | ~_PAGE_RW) & pte = __pte_ma(((pte_val_ma(*ptep) & _PAGE_RW) | ~_PAGE_RW) &
pte_val_ma(pte)); pte_val_ma(pte));
#endif #endif
native_set_pte(ptep, pte); __xen_set_pte(ptep, pte);
} }
/* Early in boot, while setting up the initial pagetable, assume /* Early in boot, while setting up the initial pagetable, assume