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PCI: designware-ep: Configure Resizable BAR cap to advertise the smallest size

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Configure the Resizable BAR capability to advertise the smallest size
(1MB) for a couple of reasons:

- Host side resource allocation of BAR fails for larger sizes
- Endpoint function driver does not allocate memory for all supported
  sizes in the Resizable BAR capability.

If and when there is a usecase required to add more flexibility using
the Resizable BAR capability, this can be revisited.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
[lorenzo.pieralisi@arm.com: updated commit log]
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
This commit is contained in:
Kishon Vijay Abraham I 2019-03-25 15:09:44 +05:30 committed by Lorenzo Pieralisi
parent 23284ad677
commit fc9a77040b
1 changed files with 34 additions and 0 deletions
repo.diff.show_diff_stats Download patch file Download diff file Expand all files Collapse all files

34
drivers/pci/controller/dwc/pcie-designware-ep.c
View file

@ -504,10 +504,32 @@ void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
pci_epc_mem_exit(epc); pci_epc_mem_exit(epc);
} }
static unsigned int dw_pcie_ep_find_ext_capability(struct dw_pcie *pci, int cap)
{
u32 header;
int pos = PCI_CFG_SPACE_SIZE;
while (pos) {
header = dw_pcie_readl_dbi(pci, pos);
if (PCI_EXT_CAP_ID(header) == cap)
return pos;
pos = PCI_EXT_CAP_NEXT(header);
if (!pos)
break;
}
return 0;
}
int dw_pcie_ep_init(struct dw_pcie_ep *ep) int dw_pcie_ep_init(struct dw_pcie_ep *ep)
{ {
int i;
int ret; int ret;
u32 reg;
void *addr; void *addr;
unsigned int nbars;
unsigned int offset;
struct pci_epc *epc; struct pci_epc *epc;
struct dw_pcie *pci = to_dw_pcie_from_ep(ep); struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
struct device *dev = pci->dev; struct device *dev = pci->dev;
@ -591,6 +613,18 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
ep->msix_cap = dw_pcie_ep_find_capability(pci, PCI_CAP_ID_MSIX); ep->msix_cap = dw_pcie_ep_find_capability(pci, PCI_CAP_ID_MSIX);
offset = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR);
if (offset) {
reg = dw_pcie_readl_dbi(pci, offset + PCI_REBAR_CTRL);
nbars = (reg & PCI_REBAR_CTRL_NBAR_MASK) >>
PCI_REBAR_CTRL_NBAR_SHIFT;
dw_pcie_dbi_ro_wr_en(pci);
for (i = 0; i < nbars; i++, offset += PCI_REBAR_CTRL)
dw_pcie_writel_dbi(pci, offset + PCI_REBAR_CAP, 0x0);
dw_pcie_dbi_ro_wr_dis(pci);
}
dw_pcie_setup(pci); dw_pcie_setup(pci);
return 0; return 0;