forked from mirrors/linux
		
	 109eb29172
			
		
	
	
		109eb29172
		
	
	
	
	
		
			
			It was observed that Tx performance was inconsistent across all queues
and/or VSIs and that it was directly connected to existing 9-layer
topology of the Tx scheduler.
Introduce new private devlink param - tx_scheduling_layers. This parameter
gives user flexibility to choose the 5-layer transmit scheduler topology
which helps to smooth out the transmit performance.
Allowed parameter values are 5 and 9.
Example usage:
Show:
devlink dev param show pci/0000:4b:00.0 name tx_scheduling_layers
pci/0000:4b:00.0:
  name tx_scheduling_layers type driver-specific
    values:
      cmode permanent value 9
Set:
devlink dev param set pci/0000:4b:00.0 name tx_scheduling_layers value 5
cmode permanent
devlink dev param set pci/0000:4b:00.0 name tx_scheduling_layers value 9
cmode permanent
Signed-off-by: Lukasz Czapnik <lukasz.czapnik@intel.com>
Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com>
Co-developed-by: Mateusz Polchlopek <mateusz.polchlopek@intel.com>
Signed-off-by: Mateusz Polchlopek <mateusz.polchlopek@intel.com>
Tested-by: Pucha Himasekhar Reddy <himasekharx.reddy.pucha@intel.com>
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
		
	
			
		
			
				
	
	
		
			49 lines
		
	
	
	
		
			2.1 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			49 lines
		
	
	
	
		
			2.1 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /* SPDX-License-Identifier: GPL-2.0 */
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| /* Copyright (c) 2019, Intel Corporation. */
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| 
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| #ifndef _ICE_NVM_H_
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| #define _ICE_NVM_H_
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| 
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| struct ice_orom_civd_info {
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| 	u8 signature[4];	/* Must match ASCII '$CIV' characters */
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| 	u8 checksum;		/* Simple modulo 256 sum of all structure bytes must equal 0 */
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| 	__le32 combo_ver;	/* Combo Image Version number */
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| 	u8 combo_name_len;	/* Length of the unicode combo image version string, max of 32 */
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| 	__le16 combo_name[32];	/* Unicode string representing the Combo Image version */
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| } __packed;
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| 
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| int ice_acquire_nvm(struct ice_hw *hw, enum ice_aq_res_access_type access);
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| void ice_release_nvm(struct ice_hw *hw);
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| int ice_aq_read_nvm(struct ice_hw *hw, u16 module_typeid, u32 offset,
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| 		    u16 length, void *data, bool last_command,
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| 		    bool read_shadow_ram, struct ice_sq_cd *cd);
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| int
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| ice_read_flat_nvm(struct ice_hw *hw, u32 offset, u32 *length, u8 *data,
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| 		  bool read_shadow_ram);
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| int
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| ice_get_pfa_module_tlv(struct ice_hw *hw, u16 *module_tlv, u16 *module_tlv_len,
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| 		       u16 module_type);
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| int ice_get_inactive_orom_ver(struct ice_hw *hw, struct ice_orom_info *orom);
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| int ice_get_inactive_nvm_ver(struct ice_hw *hw, struct ice_nvm_info *nvm);
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| int
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| ice_get_inactive_netlist_ver(struct ice_hw *hw, struct ice_netlist_info *netlist);
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| int ice_read_pba_string(struct ice_hw *hw, u8 *pba_num, u32 pba_num_size);
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| int ice_init_nvm(struct ice_hw *hw);
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| int ice_read_sr_word(struct ice_hw *hw, u16 offset, u16 *data);
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| int
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| ice_aq_update_nvm(struct ice_hw *hw, u16 module_typeid, u32 offset,
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| 		  u16 length, void *data, bool last_command, u8 command_flags,
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| 		  struct ice_sq_cd *cd);
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| int
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| ice_aq_erase_nvm(struct ice_hw *hw, u16 module_typeid, struct ice_sq_cd *cd);
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| int ice_nvm_validate_checksum(struct ice_hw *hw);
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| int ice_nvm_write_activate(struct ice_hw *hw, u16 cmd_flags, u8 *response_flags);
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| int ice_aq_nvm_update_empr(struct ice_hw *hw);
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| int
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| ice_nvm_set_pkg_data(struct ice_hw *hw, bool del_pkg_data_flag, u8 *data,
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| 		     u16 length, struct ice_sq_cd *cd);
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| int
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| ice_nvm_pass_component_tbl(struct ice_hw *hw, u8 *data, u16 length,
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| 			   u8 transfer_flag, u8 *comp_response,
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| 			   u8 *comp_response_code, struct ice_sq_cd *cd);
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| #endif /* _ICE_NVM_H_ */
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