forked from mirrors/linux
0238bcf80e
There is a single McASP on OMAP4 (and OMAP5) which is configured to only support DIT playback mode on a single serializer. Add 0x200 offset to DAT port address as the TRM suggests it. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Link: https://lore.kernel.org/r/20210705194249.2385-4-peter.ujfalusi@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
114 lines
3.3 KiB
C
114 lines
3.3 KiB
C
/*
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* TI DaVinci Audio Serial Port support
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*
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* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __DAVINCI_ASP_H
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#define __DAVINCI_ASP_H
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#include <linux/genalloc.h>
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struct davinci_mcasp_pdata {
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u32 tx_dma_offset;
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u32 rx_dma_offset;
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int asp_chan_q; /* event queue number for ASP channel */
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int ram_chan_q; /* event queue number for RAM channel */
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/*
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* Allowing this is more efficient and eliminates left and right swaps
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* caused by underruns, but will swap the left and right channels
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* when compared to previous behavior.
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*/
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unsigned enable_channel_combine:1;
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unsigned sram_size_playback;
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unsigned sram_size_capture;
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struct gen_pool *sram_pool;
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/*
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* If McBSP peripheral gets the clock from an external pin,
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* there are three chooses, that are MCBSP_CLKX, MCBSP_CLKR
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* and MCBSP_CLKS.
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* Depending on different hardware connections it is possible
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* to use this setting to change the behaviour of McBSP
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* driver.
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*/
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int clk_input_pin;
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/*
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* This flag works when both clock and FS are outputs for the cpu
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* and makes clock more accurate (FS is not symmetrical and the
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* clock is very fast.
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* The clock becoming faster is named
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* i2s continuous serial clock (I2S_SCK) and it is an externally
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* visible bit clock.
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*
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* first line : WordSelect
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* second line : ContinuousSerialClock
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* third line: SerialData
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*
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* SYMMETRICAL APPROACH:
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* _______________________ LEFT
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* _| RIGHT |______________________|
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* _ _ _ _ _ _ _ _
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* _| |_| |_ x16 _| |_| |_| |_| |_ x16 _| |_| |_
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* _ _ _ _ _ _ _ _
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* _/ \_/ \_ ... _/ \_/ \_/ \_/ \_ ... _/ \_/ \_
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* \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/
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*
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* ACCURATE CLOCK APPROACH:
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* ______________ LEFT
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* _| RIGHT |_______________________________|
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* _ _ _ _ _ _ _ _ _
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* _| |_ x16 _| |_| |_ x16 _| |_| |_| |_| |_| |_| |
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* _ _ _ _ dummy cycles
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* _/ \_ ... _/ \_/ \_ ... _/ \__________________
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* \_/ \_/ \_/ \_/
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*
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*/
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bool i2s_accurate_sck;
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/* McASP specific fields */
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int tdm_slots;
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u8 op_mode;
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u8 dismod;
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u8 num_serializer;
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u8 *serial_dir;
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u8 version;
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u8 txnumevt;
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u8 rxnumevt;
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int tx_dma_channel;
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int rx_dma_channel;
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};
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/* TODO: Fix arch/arm/mach-davinci/ users and remove this define */
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#define snd_platform_data davinci_mcasp_pdata
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enum {
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MCASP_VERSION_1 = 0, /* DM646x */
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MCASP_VERSION_2, /* DA8xx/OMAPL1x */
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MCASP_VERSION_3, /* TI81xx/AM33xx */
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MCASP_VERSION_4, /* DRA7xxx */
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MCASP_VERSION_OMAP, /* OMAP4/5 */
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};
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enum mcbsp_clk_input_pin {
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MCBSP_CLKR = 0, /* as in DM365 */
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MCBSP_CLKS,
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};
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#define INACTIVE_MODE 0
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#define TX_MODE 1
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#define RX_MODE 2
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#define DAVINCI_MCASP_IIS_MODE 0
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#define DAVINCI_MCASP_DIT_MODE 1
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#endif
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