forked from mirrors/linux
642af0f92c
There exists several examples today of devices that embed an ethernet PHY or PCS directly inside an SoC. In this situation, either the device is controlled through a vendor-specific register set, or sometimes exposes the standard 802.3 registers that are typically accessed over MDIO. As phylib and phylink are designed to use mdiodevices, this driver allows creating a virtual MDIO bus, that translates mdiodev register accesses to regmap accesses. The reason we use regmap is because there are at least 3 such devices known today, 2 of them are Altera TSE PCS's, memory-mapped, exposed with a 4-byte stride in stmmac's dwmac-socfpga variant, and a 2-byte stride in altera-tse. The other one (nxp,sja1110-base-tx-mdio) is exposed over SPI. Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com> Reviewed-by: Simon Horman <simon.horman@corigine.com> Signed-off-by: David S. Miller <davem@davemloft.net>
93 lines
2.1 KiB
C
93 lines
2.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/* Driver for MMIO-Mapped MDIO devices. Some IPs expose internal PHYs or PCS
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* within the MMIO-mapped area
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*
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* Copyright (C) 2023 Maxime Chevallier <maxime.chevallier@bootlin.com>
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*/
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#include <linux/bitfield.h>
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#include <linux/delay.h>
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#include <linux/mdio.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_mdio.h>
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#include <linux/phy.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/mdio/mdio-regmap.h>
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#define DRV_NAME "mdio-regmap"
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struct mdio_regmap_priv {
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struct regmap *regmap;
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u8 valid_addr;
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};
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static int mdio_regmap_read_c22(struct mii_bus *bus, int addr, int regnum)
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{
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struct mdio_regmap_priv *ctx = bus->priv;
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unsigned int val;
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int ret;
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if (ctx->valid_addr != addr)
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return -ENODEV;
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ret = regmap_read(ctx->regmap, regnum, &val);
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if (ret < 0)
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return ret;
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return val;
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}
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static int mdio_regmap_write_c22(struct mii_bus *bus, int addr, int regnum,
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u16 val)
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{
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struct mdio_regmap_priv *ctx = bus->priv;
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if (ctx->valid_addr != addr)
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return -ENODEV;
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return regmap_write(ctx->regmap, regnum, val);
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}
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struct mii_bus *devm_mdio_regmap_register(struct device *dev,
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const struct mdio_regmap_config *config)
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{
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struct mdio_regmap_priv *mr;
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struct mii_bus *mii;
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int rc;
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if (!config->parent)
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return ERR_PTR(-EINVAL);
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mii = devm_mdiobus_alloc_size(config->parent, sizeof(*mr));
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if (!mii)
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return ERR_PTR(-ENOMEM);
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mr = mii->priv;
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mr->regmap = config->regmap;
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mr->valid_addr = config->valid_addr;
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mii->name = DRV_NAME;
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strscpy(mii->id, config->name, MII_BUS_ID_SIZE);
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mii->parent = config->parent;
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mii->read = mdio_regmap_read_c22;
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mii->write = mdio_regmap_write_c22;
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if (config->autoscan)
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mii->phy_mask = ~BIT(config->valid_addr);
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else
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mii->phy_mask = ~0;
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rc = devm_mdiobus_register(dev, mii);
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if (rc) {
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dev_err(config->parent, "Cannot register MDIO bus![%s] (%d)\n", mii->id, rc);
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return ERR_PTR(rc);
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}
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return mii;
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}
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EXPORT_SYMBOL_GPL(devm_mdio_regmap_register);
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MODULE_DESCRIPTION("MDIO API over regmap");
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MODULE_AUTHOR("Maxime Chevallier <maxime.chevallier@bootlin.com>");
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MODULE_LICENSE("GPL");
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