forked from mirrors/linux
35e237b3d5
Add crypto clock and reset ID definitions for ipq9574. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230526161129.1454-2-quic_anusha@quicinc.com
165 lines
5.5 KiB
C
165 lines
5.5 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2018-2023, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_RESET_IPQ_GCC_9574_H
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#define _DT_BINDINGS_RESET_IPQ_GCC_9574_H
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#define GCC_ADSS_BCR 0
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#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 1
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#define GCC_BLSP1_BCR 2
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#define GCC_BLSP1_QUP1_BCR 3
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#define GCC_BLSP1_QUP2_BCR 4
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#define GCC_BLSP1_QUP3_BCR 5
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#define GCC_BLSP1_QUP4_BCR 6
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#define GCC_BLSP1_QUP5_BCR 7
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#define GCC_BLSP1_QUP6_BCR 8
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#define GCC_BLSP1_UART1_BCR 9
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#define GCC_BLSP1_UART2_BCR 10
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#define GCC_BLSP1_UART3_BCR 11
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#define GCC_BLSP1_UART4_BCR 12
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#define GCC_BLSP1_UART5_BCR 13
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#define GCC_BLSP1_UART6_BCR 14
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#define GCC_BOOT_ROM_BCR 15
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#define GCC_MDIO_BCR 16
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#define GCC_NSS_BCR 17
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#define GCC_NSS_TBU_BCR 18
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#define GCC_PCIE0_BCR 19
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#define GCC_PCIE0_LINK_DOWN_BCR 20
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#define GCC_PCIE0_PHY_BCR 21
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#define GCC_PCIE0PHY_PHY_BCR 22
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#define GCC_PCIE1_BCR 23
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#define GCC_PCIE1_LINK_DOWN_BCR 24
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#define GCC_PCIE1_PHY_BCR 25
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#define GCC_PCIE1PHY_PHY_BCR 26
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#define GCC_PCIE2_BCR 27
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#define GCC_PCIE2_LINK_DOWN_BCR 28
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#define GCC_PCIE2_PHY_BCR 29
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#define GCC_PCIE2PHY_PHY_BCR 30
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#define GCC_PCIE3_BCR 31
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#define GCC_PCIE3_LINK_DOWN_BCR 32
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#define GCC_PCIE3_PHY_BCR 33
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#define GCC_PCIE3PHY_PHY_BCR 34
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#define GCC_PRNG_BCR 35
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#define GCC_QUSB2_0_PHY_BCR 36
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#define GCC_SDCC_BCR 37
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#define GCC_TLMM_BCR 38
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#define GCC_UNIPHY0_BCR 39
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#define GCC_UNIPHY1_BCR 40
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#define GCC_UNIPHY2_BCR 41
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#define GCC_USB0_PHY_BCR 42
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#define GCC_USB3PHY_0_PHY_BCR 43
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#define GCC_USB_BCR 44
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#define GCC_ANOC0_TBU_BCR 45
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#define GCC_ANOC1_TBU_BCR 46
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#define GCC_ANOC_BCR 47
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#define GCC_APSS_TCU_BCR 48
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#define GCC_CMN_BLK_BCR 49
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#define GCC_CMN_BLK_AHB_ARES 50
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#define GCC_CMN_BLK_SYS_ARES 51
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#define GCC_CMN_BLK_APU_ARES 52
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#define GCC_DCC_BCR 53
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#define GCC_DDRSS_BCR 54
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#define GCC_IMEM_BCR 55
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#define GCC_LPASS_BCR 56
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#define GCC_MPM_BCR 57
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#define GCC_MSG_RAM_BCR 58
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#define GCC_NSSNOC_MEMNOC_1_ARES 59
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#define GCC_NSSNOC_PCNOC_1_ARES 60
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#define GCC_NSSNOC_SNOC_1_ARES 61
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#define GCC_NSSNOC_XO_DCD_ARES 62
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#define GCC_NSSNOC_TS_ARES 63
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#define GCC_NSSCC_ARES 64
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#define GCC_NSSNOC_NSSCC_ARES 65
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#define GCC_NSSNOC_ATB_ARES 66
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#define GCC_NSSNOC_MEMNOC_ARES 67
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#define GCC_NSSNOC_QOSGEN_REF_ARES 68
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#define GCC_NSSNOC_SNOC_ARES 69
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#define GCC_NSSNOC_TIMEOUT_REF_ARES 70
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#define GCC_NSS_CFG_ARES 71
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#define GCC_UBI0_DBG_ARES 72
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#define GCC_PCIE0_AHB_ARES 73
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#define GCC_PCIE0_AUX_ARES 74
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#define GCC_PCIE0_AXI_M_ARES 75
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#define GCC_PCIE0_AXI_M_STICKY_ARES 76
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#define GCC_PCIE0_AXI_S_ARES 77
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#define GCC_PCIE0_AXI_S_STICKY_ARES 78
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#define GCC_PCIE0_CORE_STICKY_ARES 79
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#define GCC_PCIE0_PIPE_ARES 80
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#define GCC_PCIE1_AHB_ARES 81
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#define GCC_PCIE1_AUX_ARES 82
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#define GCC_PCIE1_AXI_M_ARES 83
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#define GCC_PCIE1_AXI_M_STICKY_ARES 84
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#define GCC_PCIE1_AXI_S_ARES 85
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#define GCC_PCIE1_AXI_S_STICKY_ARES 86
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#define GCC_PCIE1_CORE_STICKY_ARES 87
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#define GCC_PCIE1_PIPE_ARES 88
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#define GCC_PCIE2_AHB_ARES 89
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#define GCC_PCIE2_AUX_ARES 90
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#define GCC_PCIE2_AXI_M_ARES 91
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#define GCC_PCIE2_AXI_M_STICKY_ARES 92
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#define GCC_PCIE2_AXI_S_ARES 93
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#define GCC_PCIE2_AXI_S_STICKY_ARES 94
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#define GCC_PCIE2_CORE_STICKY_ARES 95
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#define GCC_PCIE2_PIPE_ARES 96
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#define GCC_PCIE3_AHB_ARES 97
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#define GCC_PCIE3_AUX_ARES 98
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#define GCC_PCIE3_AXI_M_ARES 99
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#define GCC_PCIE3_AXI_M_STICKY_ARES 100
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#define GCC_PCIE3_AXI_S_ARES 101
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#define GCC_PCIE3_AXI_S_STICKY_ARES 102
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#define GCC_PCIE3_CORE_STICKY_ARES 103
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#define GCC_PCIE3_PIPE_ARES 104
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#define GCC_PCNOC_BCR 105
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#define GCC_PCNOC_BUS_TIMEOUT0_BCR 106
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#define GCC_PCNOC_BUS_TIMEOUT1_BCR 107
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#define GCC_PCNOC_BUS_TIMEOUT2_BCR 108
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#define GCC_PCNOC_BUS_TIMEOUT3_BCR 109
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#define GCC_PCNOC_BUS_TIMEOUT4_BCR 110
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#define GCC_PCNOC_BUS_TIMEOUT5_BCR 111
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#define GCC_PCNOC_BUS_TIMEOUT6_BCR 112
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#define GCC_PCNOC_BUS_TIMEOUT7_BCR 113
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#define GCC_PCNOC_BUS_TIMEOUT8_BCR 114
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#define GCC_PCNOC_BUS_TIMEOUT9_BCR 115
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#define GCC_PCNOC_TBU_BCR 116
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#define GCC_Q6SS_DBG_ARES 117
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#define GCC_Q6_AHB_ARES 118
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#define GCC_Q6_AHB_S_ARES 119
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#define GCC_Q6_AXIM2_ARES 120
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#define GCC_Q6_AXIM_ARES 121
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#define GCC_QDSS_BCR 122
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#define GCC_QPIC_BCR 123
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#define GCC_QPIC_AHB_ARES 124
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#define GCC_QPIC_ARES 125
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#define GCC_RBCPR_BCR 126
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#define GCC_RBCPR_MX_BCR 127
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#define GCC_SEC_CTRL_BCR 128
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#define GCC_SMMU_CFG_BCR 129
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#define GCC_SNOC_BCR 130
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#define GCC_SPDM_BCR 131
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#define GCC_TME_BCR 132
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#define GCC_UNIPHY0_SYS_RESET 133
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#define GCC_UNIPHY0_AHB_RESET 134
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#define GCC_UNIPHY0_XPCS_RESET 135
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#define GCC_UNIPHY1_SYS_RESET 136
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#define GCC_UNIPHY1_AHB_RESET 137
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#define GCC_UNIPHY1_XPCS_RESET 138
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#define GCC_UNIPHY2_SYS_RESET 139
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#define GCC_UNIPHY2_AHB_RESET 140
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#define GCC_UNIPHY2_XPCS_RESET 141
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#define GCC_USB_MISC_RESET 142
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#define GCC_WCSSAON_RESET 143
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#define GCC_WCSS_ACMT_ARES 144
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#define GCC_WCSS_AHB_S_ARES 145
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#define GCC_WCSS_AXI_M_ARES 146
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#define GCC_WCSS_BCR 147
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#define GCC_WCSS_DBG_ARES 148
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#define GCC_WCSS_DBG_BDG_ARES 149
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#define GCC_WCSS_ECAHB_ARES 150
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#define GCC_WCSS_Q6_BCR 151
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#define GCC_WCSS_Q6_TBU_BCR 152
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#define GCC_TCSR_BCR 153
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#define GCC_CRYPTO_BCR 154
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#endif
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