forked from mirrors/linux
1ea0d14e48
The Intel Optimization Reference Guide says: In Intel Atom microarchitecture, the address generation unit assumes that the segment base will be 0 by default. Non-zero segment base will cause load and store operations to experience a delay. - If the segment base isn't aligned to a cache line boundary, the max throughput of memory operations is reduced to one [e]very 9 cycles. [...] Assembly/Compiler Coding Rule 15. (H impact, ML generality) For Intel Atom processors, use segments with base set to 0 whenever possible; avoid non-zero segment base address that is not aligned to cache line boundary at all cost. We can't avoid having a non-zero base for the stack-protector segment, but we can make it cache-aligned. Signed-off-by: Jeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com> Cc: <stable@kernel.org> LKML-Reference: <4AA01893.6000507@goop.org> Signed-off-by: Ingo Molnar <mingo@elte.hu>
122 lines
3.8 KiB
C
122 lines
3.8 KiB
C
/*
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* GCC stack protector support.
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*
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* Stack protector works by putting predefined pattern at the start of
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* the stack frame and verifying that it hasn't been overwritten when
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* returning from the function. The pattern is called stack canary
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* and unfortunately gcc requires it to be at a fixed offset from %gs.
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* On x86_64, the offset is 40 bytes and on x86_32 20 bytes. x86_64
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* and x86_32 use segment registers differently and thus handles this
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* requirement differently.
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*
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* On x86_64, %gs is shared by percpu area and stack canary. All
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* percpu symbols are zero based and %gs points to the base of percpu
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* area. The first occupant of the percpu area is always
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* irq_stack_union which contains stack_canary at offset 40. Userland
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* %gs is always saved and restored on kernel entry and exit using
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* swapgs, so stack protector doesn't add any complexity there.
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*
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* On x86_32, it's slightly more complicated. As in x86_64, %gs is
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* used for userland TLS. Unfortunately, some processors are much
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* slower at loading segment registers with different value when
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* entering and leaving the kernel, so the kernel uses %fs for percpu
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* area and manages %gs lazily so that %gs is switched only when
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* necessary, usually during task switch.
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*
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* As gcc requires the stack canary at %gs:20, %gs can't be managed
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* lazily if stack protector is enabled, so the kernel saves and
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* restores userland %gs on kernel entry and exit. This behavior is
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* controlled by CONFIG_X86_32_LAZY_GS and accessors are defined in
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* system.h to hide the details.
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*/
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#ifndef _ASM_STACKPROTECTOR_H
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#define _ASM_STACKPROTECTOR_H 1
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#ifdef CONFIG_CC_STACKPROTECTOR
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#include <asm/tsc.h>
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#include <asm/processor.h>
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#include <asm/percpu.h>
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#include <asm/system.h>
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#include <asm/desc.h>
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#include <linux/random.h>
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/*
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* 24 byte read-only segment initializer for stack canary. Linker
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* can't handle the address bit shifting. Address will be set in
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* head_32 for boot CPU and setup_per_cpu_areas() for others.
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*/
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#define GDT_STACK_CANARY_INIT \
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[GDT_ENTRY_STACK_CANARY] = GDT_ENTRY_INIT(0x4090, 0, 0x18),
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/*
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* Initialize the stackprotector canary value.
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*
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* NOTE: this must only be called from functions that never return,
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* and it must always be inlined.
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*/
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static __always_inline void boot_init_stack_canary(void)
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{
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u64 canary;
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u64 tsc;
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#ifdef CONFIG_X86_64
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BUILD_BUG_ON(offsetof(union irq_stack_union, stack_canary) != 40);
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#endif
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/*
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* We both use the random pool and the current TSC as a source
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* of randomness. The TSC only matters for very early init,
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* there it already has some randomness on most systems. Later
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* on during the bootup the random pool has true entropy too.
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*/
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get_random_bytes(&canary, sizeof(canary));
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tsc = __native_read_tsc();
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canary += tsc + (tsc << 32UL);
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current->stack_canary = canary;
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#ifdef CONFIG_X86_64
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percpu_write(irq_stack_union.stack_canary, canary);
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#else
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percpu_write(stack_canary.canary, canary);
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#endif
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}
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static inline void setup_stack_canary_segment(int cpu)
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{
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#ifdef CONFIG_X86_32
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unsigned long canary = (unsigned long)&per_cpu(stack_canary, cpu);
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struct desc_struct *gdt_table = get_cpu_gdt_table(cpu);
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struct desc_struct desc;
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desc = gdt_table[GDT_ENTRY_STACK_CANARY];
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set_desc_base(&desc, canary);
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write_gdt_entry(gdt_table, GDT_ENTRY_STACK_CANARY, &desc, DESCTYPE_S);
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#endif
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}
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static inline void load_stack_canary_segment(void)
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{
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#ifdef CONFIG_X86_32
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asm("mov %0, %%gs" : : "r" (__KERNEL_STACK_CANARY) : "memory");
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#endif
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}
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#else /* CC_STACKPROTECTOR */
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#define GDT_STACK_CANARY_INIT
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/* dummy boot_init_stack_canary() is defined in linux/stackprotector.h */
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static inline void setup_stack_canary_segment(int cpu)
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{ }
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static inline void load_stack_canary_segment(void)
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{
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#ifdef CONFIG_X86_32
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asm volatile ("mov %0, %%gs" : : "r" (0));
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#endif
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}
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#endif /* CC_STACKPROTECTOR */
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#endif /* _ASM_STACKPROTECTOR_H */
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