forked from mirrors/linux
2a2ac8a701
The automatic "save & restore" of interrupt context is a POWER10/XIVE2
feature exploited by KVM under the PowerNV platform. It is not
available under pSeries and the associated toggle should not be
exposed under the XIVE debugfs directory.
Introduce a platform handler for debugfs initialization and move the
'save-restore' entry under the native (PowerNV) backend to fix compile
when !CONFIG_PPC_POWERNV.
Fixes: 1e7684dc4f ("powerpc/xive: Add a debugfs toggle for save-restore")
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20211201165418.1041842-1-clg@kaod.org
78 lines
2.3 KiB
C
78 lines
2.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright 2016,2017 IBM Corporation.
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*/
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#ifndef __XIVE_INTERNAL_H
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#define __XIVE_INTERNAL_H
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/*
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* A "disabled" interrupt should never fire, to catch problems
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* we set its logical number to this
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*/
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#define XIVE_BAD_IRQ 0x7fffffff
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#define XIVE_MAX_IRQ (XIVE_BAD_IRQ - 1)
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/* Each CPU carry one of these with various per-CPU state */
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struct xive_cpu {
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#ifdef CONFIG_SMP
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/* HW irq number and data of IPI */
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u32 hw_ipi;
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struct xive_irq_data ipi_data;
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#endif /* CONFIG_SMP */
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int chip_id;
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/* Queue datas. Only one is populated */
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#define XIVE_MAX_QUEUES 8
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struct xive_q queue[XIVE_MAX_QUEUES];
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/*
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* Pending mask. Each bit corresponds to a priority that
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* potentially has pending interrupts.
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*/
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u8 pending_prio;
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/* Cache of HW CPPR */
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u8 cppr;
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};
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/* Backend ops */
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struct xive_ops {
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int (*populate_irq_data)(u32 hw_irq, struct xive_irq_data *data);
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int (*configure_irq)(u32 hw_irq, u32 target, u8 prio, u32 sw_irq);
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int (*get_irq_config)(u32 hw_irq, u32 *target, u8 *prio,
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u32 *sw_irq);
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int (*setup_queue)(unsigned int cpu, struct xive_cpu *xc, u8 prio);
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void (*cleanup_queue)(unsigned int cpu, struct xive_cpu *xc, u8 prio);
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void (*prepare_cpu)(unsigned int cpu, struct xive_cpu *xc);
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void (*setup_cpu)(unsigned int cpu, struct xive_cpu *xc);
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void (*teardown_cpu)(unsigned int cpu, struct xive_cpu *xc);
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bool (*match)(struct device_node *np);
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void (*shutdown)(void);
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void (*update_pending)(struct xive_cpu *xc);
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void (*sync_source)(u32 hw_irq);
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u64 (*esb_rw)(u32 hw_irq, u32 offset, u64 data, bool write);
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#ifdef CONFIG_SMP
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int (*get_ipi)(unsigned int cpu, struct xive_cpu *xc);
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void (*put_ipi)(unsigned int cpu, struct xive_cpu *xc);
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#endif
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int (*debug_show)(struct seq_file *m, void *private);
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int (*debug_create)(struct dentry *xive_dir);
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const char *name;
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};
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bool xive_core_init(struct device_node *np, const struct xive_ops *ops,
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void __iomem *area, u32 offset, u8 max_prio);
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__be32 *xive_queue_page_alloc(unsigned int cpu, u32 queue_shift);
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int xive_core_debug_init(void);
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static inline u32 xive_alloc_order(u32 queue_shift)
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{
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return (queue_shift > PAGE_SHIFT) ? (queue_shift - PAGE_SHIFT) : 0;
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}
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extern bool xive_cmdline_disabled;
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extern bool xive_has_save_restore;
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#endif /* __XIVE_INTERNAL_H */
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