forked from mirrors/linux
		
	With 16 channel pwm support, we're registering two instances of pwm_chip
with 8 channels each. We need to update PM functions to use both instances
of pwm_chip during power state transitions.
Introduce struct dwc_pwm_drvdata and use it as driver_data, which will
maintain both instances of pwm_chip along with dwc_pwm_info and allow us
to use them inside suspend/resume handles.
Fixes: ebf2c89eb9 ("pwm: dwc: Add 16 channel support for Intel Elkhart Lake")
Signed-off-by: Raag Jadav <raag.jadav@intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20240415074051.14681-1-raag.jadav@intel.com
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
		
	
			
		
			
				
	
	
		
			174 lines
		
	
	
	
		
			4.2 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			174 lines
		
	
	
	
		
			4.2 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
// SPDX-License-Identifier: GPL-2.0
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/*
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 * DesignWare PWM Controller driver (PCI part)
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 *
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 * Copyright (C) 2018-2020 Intel Corporation
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 *
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 * Author: Felipe Balbi (Intel)
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 * Author: Jarkko Nikula <jarkko.nikula@linux.intel.com>
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 * Author: Raymond Tan <raymond.tan@intel.com>
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 *
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 * Limitations:
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 * - The hardware cannot generate a 0 % or 100 % duty cycle. Both high and low
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 *   periods are one or more input clock periods long.
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 */
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#define DEFAULT_MOUDLE_NAMESPACE dwc_pwm
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#include <linux/bitops.h>
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#include <linux/export.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/pm_runtime.h>
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#include <linux/pwm.h>
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#include "pwm-dwc.h"
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/* Elkhart Lake */
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static const struct dwc_pwm_info ehl_pwm_info = {
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	.nr = 2,
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	.size = 0x1000,
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};
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static int dwc_pwm_init_one(struct device *dev, struct dwc_pwm_drvdata *ddata, unsigned int idx)
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{
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	struct pwm_chip *chip;
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	struct dwc_pwm *dwc;
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	int ret;
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	chip = dwc_pwm_alloc(dev);
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	if (IS_ERR(chip))
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		return PTR_ERR(chip);
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	dwc = to_dwc_pwm(chip);
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	dwc->base = ddata->io_base + (ddata->info->size * idx);
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	ret = devm_pwmchip_add(dev, chip);
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	if (ret)
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		return ret;
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	ddata->chips[idx] = chip;
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	return 0;
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}
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static int dwc_pwm_probe(struct pci_dev *pci, const struct pci_device_id *id)
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{
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	const struct dwc_pwm_info *info;
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	struct device *dev = &pci->dev;
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	struct dwc_pwm_drvdata *ddata;
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	unsigned int idx;
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	int ret;
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	ret = pcim_enable_device(pci);
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	if (ret)
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		return dev_err_probe(dev, ret, "Failed to enable device\n");
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	pci_set_master(pci);
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	ret = pcim_iomap_regions(pci, BIT(0), pci_name(pci));
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	if (ret)
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		return dev_err_probe(dev, ret, "Failed to iomap PCI BAR\n");
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	info = (const struct dwc_pwm_info *)id->driver_data;
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	ddata = devm_kzalloc(dev, struct_size(ddata, chips, info->nr), GFP_KERNEL);
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	if (!ddata)
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		return -ENOMEM;
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	/*
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	 * No need to check for pcim_iomap_table() failure,
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	 * pcim_iomap_regions() already does it for us.
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	 */
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	ddata->io_base = pcim_iomap_table(pci)[0];
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	ddata->info = info;
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	for (idx = 0; idx < ddata->info->nr; idx++) {
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		ret = dwc_pwm_init_one(dev, ddata, idx);
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		if (ret)
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			return ret;
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	}
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	dev_set_drvdata(dev, ddata);
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	pm_runtime_put(dev);
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	pm_runtime_allow(dev);
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	return 0;
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}
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static void dwc_pwm_remove(struct pci_dev *pci)
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{
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	pm_runtime_forbid(&pci->dev);
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	pm_runtime_get_noresume(&pci->dev);
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}
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static int dwc_pwm_suspend(struct device *dev)
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{
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	struct dwc_pwm_drvdata *ddata = dev_get_drvdata(dev);
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	unsigned int idx;
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	for (idx = 0; idx < ddata->info->nr; idx++) {
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		struct pwm_chip *chip = ddata->chips[idx];
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		struct dwc_pwm *dwc = to_dwc_pwm(chip);
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		unsigned int i;
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		for (i = 0; i < DWC_TIMERS_TOTAL; i++) {
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			if (chip->pwms[i].state.enabled) {
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				dev_err(dev, "PWM %u in use by consumer (%s)\n",
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					i, chip->pwms[i].label);
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				return -EBUSY;
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			}
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			dwc->ctx[i].cnt = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(i));
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			dwc->ctx[i].cnt2 = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(i));
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			dwc->ctx[i].ctrl = dwc_pwm_readl(dwc, DWC_TIM_CTRL(i));
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		}
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	}
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	return 0;
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}
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static int dwc_pwm_resume(struct device *dev)
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{
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	struct dwc_pwm_drvdata *ddata = dev_get_drvdata(dev);
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	unsigned int idx;
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	for (idx = 0; idx < ddata->info->nr; idx++) {
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		struct pwm_chip *chip = ddata->chips[idx];
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		struct dwc_pwm *dwc = to_dwc_pwm(chip);
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		unsigned int i;
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		for (i = 0; i < DWC_TIMERS_TOTAL; i++) {
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			dwc_pwm_writel(dwc, dwc->ctx[i].cnt, DWC_TIM_LD_CNT(i));
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			dwc_pwm_writel(dwc, dwc->ctx[i].cnt2, DWC_TIM_LD_CNT2(i));
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			dwc_pwm_writel(dwc, dwc->ctx[i].ctrl, DWC_TIM_CTRL(i));
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		}
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	}
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	return 0;
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}
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static DEFINE_SIMPLE_DEV_PM_OPS(dwc_pwm_pm_ops, dwc_pwm_suspend, dwc_pwm_resume);
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static const struct pci_device_id dwc_pwm_id_table[] = {
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	{ PCI_VDEVICE(INTEL, 0x4bb7), (kernel_ulong_t)&ehl_pwm_info },
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	{  }	/* Terminating Entry */
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};
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MODULE_DEVICE_TABLE(pci, dwc_pwm_id_table);
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static struct pci_driver dwc_pwm_driver = {
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	.name = "pwm-dwc",
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	.probe = dwc_pwm_probe,
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	.remove = dwc_pwm_remove,
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	.id_table = dwc_pwm_id_table,
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	.driver = {
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		.pm = pm_sleep_ptr(&dwc_pwm_pm_ops),
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	},
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};
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module_pci_driver(dwc_pwm_driver);
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MODULE_AUTHOR("Felipe Balbi (Intel)");
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MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@linux.intel.com>");
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MODULE_AUTHOR("Raymond Tan <raymond.tan@intel.com>");
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MODULE_DESCRIPTION("DesignWare PWM Controller");
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MODULE_LICENSE("GPL");
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