forked from mirrors/linux
		
	 6120e5d821
			
		
	
	
		6120e5d821
		
	
	
	
	
		
			
			Add device tree bindings for the Qualcomm MSM8974 interconnect providers that support setting system bandwidth requirements between various network-on-chip fabrics. Signed-off-by: Brian Masney <masneyb@onstation.org> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20191024103054.9770-2-masneyb@onstation.org Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Link: https://lore.kernel.org/r/20191108125349.24191-2-georgi.djakov@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
		
			
				
	
	
		
			146 lines
		
	
	
	
		
			4.1 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			146 lines
		
	
	
	
		
			4.1 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */
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| /*
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|  * Qualcomm msm8974 interconnect IDs
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|  *
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|  * Copyright (c) 2019 Brian Masney <masneyb@onstation.org>
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|  */
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| 
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| #ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MSM8974_H
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| #define __DT_BINDINGS_INTERCONNECT_QCOM_MSM8974_H
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| 
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| #define BIMC_MAS_AMPSS_M0		0
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| #define BIMC_MAS_AMPSS_M1		1
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| #define BIMC_MAS_MSS_PROC		2
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| #define BIMC_TO_MNOC			3
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| #define BIMC_TO_SNOC			4
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| #define BIMC_SLV_EBI_CH0		5
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| #define BIMC_SLV_AMPSS_L2		6
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| 
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| #define CNOC_MAS_RPM_INST		0
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| #define CNOC_MAS_RPM_DATA		1
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| #define CNOC_MAS_RPM_SYS		2
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| #define CNOC_MAS_DEHR			3
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| #define CNOC_MAS_QDSS_DAP		4
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| #define CNOC_MAS_SPDM			5
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| #define CNOC_MAS_TIC			6
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| #define CNOC_SLV_CLK_CTL		7
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| #define CNOC_SLV_CNOC_MSS		8
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| #define CNOC_SLV_SECURITY		9
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| #define CNOC_SLV_TCSR			10
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| #define CNOC_SLV_TLMM			11
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| #define CNOC_SLV_CRYPTO_0_CFG		12
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| #define CNOC_SLV_CRYPTO_1_CFG		13
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| #define CNOC_SLV_IMEM_CFG		14
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| #define CNOC_SLV_MESSAGE_RAM		15
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| #define CNOC_SLV_BIMC_CFG		16
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| #define CNOC_SLV_BOOT_ROM		17
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| #define CNOC_SLV_PMIC_ARB		18
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| #define CNOC_SLV_SPDM_WRAPPER		19
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| #define CNOC_SLV_DEHR_CFG		20
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| #define CNOC_SLV_MPM			21
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| #define CNOC_SLV_QDSS_CFG		22
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| #define CNOC_SLV_RBCPR_CFG		23
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| #define CNOC_SLV_RBCPR_QDSS_APU_CFG	24
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| #define CNOC_TO_SNOC			25
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| #define CNOC_SLV_CNOC_ONOC_CFG		26
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| #define CNOC_SLV_CNOC_MNOC_MMSS_CFG	27
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| #define CNOC_SLV_CNOC_MNOC_CFG		28
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| #define CNOC_SLV_PNOC_CFG		29
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| #define CNOC_SLV_SNOC_MPU_CFG		30
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| #define CNOC_SLV_SNOC_CFG		31
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| #define CNOC_SLV_EBI1_DLL_CFG		32
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| #define CNOC_SLV_PHY_APU_CFG		33
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| #define CNOC_SLV_EBI1_PHY_CFG		34
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| #define CNOC_SLV_RPM			35
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| #define CNOC_SLV_SERVICE_CNOC		36
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| 
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| #define MNOC_MAS_GRAPHICS_3D		0
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| #define MNOC_MAS_JPEG			1
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| #define MNOC_MAS_MDP_PORT0		2
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| #define MNOC_MAS_VIDEO_P0		3
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| #define MNOC_MAS_VIDEO_P1		4
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| #define MNOC_MAS_VFE			5
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| #define MNOC_TO_CNOC			6
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| #define MNOC_TO_BIMC			7
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| #define MNOC_SLV_CAMERA_CFG		8
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| #define MNOC_SLV_DISPLAY_CFG		9
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| #define MNOC_SLV_OCMEM_CFG		10
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| #define MNOC_SLV_CPR_CFG		11
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| #define MNOC_SLV_CPR_XPU_CFG		12
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| #define MNOC_SLV_MISC_CFG		13
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| #define MNOC_SLV_MISC_XPU_CFG		14
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| #define MNOC_SLV_VENUS_CFG		15
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| #define MNOC_SLV_GRAPHICS_3D_CFG	16
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| #define MNOC_SLV_MMSS_CLK_CFG		17
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| #define MNOC_SLV_MMSS_CLK_XPU_CFG	18
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| #define MNOC_SLV_MNOC_MPU_CFG		19
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| #define MNOC_SLV_ONOC_MPU_CFG		20
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| #define MNOC_SLV_SERVICE_MNOC		21
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| 
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| #define OCMEM_NOC_TO_OCMEM_VNOC		0
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| #define OCMEM_MAS_JPEG_OCMEM		1
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| #define OCMEM_MAS_MDP_OCMEM		2
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| #define OCMEM_MAS_VIDEO_P0_OCMEM	3
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| #define OCMEM_MAS_VIDEO_P1_OCMEM	4
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| #define OCMEM_MAS_VFE_OCMEM		5
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| #define OCMEM_MAS_CNOC_ONOC_CFG		6
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| #define OCMEM_SLV_SERVICE_ONOC		7
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| #define OCMEM_VNOC_TO_SNOC		8
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| #define OCMEM_VNOC_TO_OCMEM_NOC		9
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| #define OCMEM_VNOC_MAS_GFX3D		10
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| #define OCMEM_SLV_OCMEM			11
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| 
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| #define PNOC_MAS_PNOC_CFG		0
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| #define PNOC_MAS_SDCC_1			1
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| #define PNOC_MAS_SDCC_3			2
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| #define PNOC_MAS_SDCC_4			3
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| #define PNOC_MAS_SDCC_2			4
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| #define PNOC_MAS_TSIF			5
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| #define PNOC_MAS_BAM_DMA		6
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| #define PNOC_MAS_BLSP_2			7
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| #define PNOC_MAS_USB_HSIC		8
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| #define PNOC_MAS_BLSP_1			9
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| #define PNOC_MAS_USB_HS			10
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| #define PNOC_TO_SNOC			11
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| #define PNOC_SLV_SDCC_1			12
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| #define PNOC_SLV_SDCC_3			13
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| #define PNOC_SLV_SDCC_2			14
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| #define PNOC_SLV_SDCC_4			15
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| #define PNOC_SLV_TSIF			16
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| #define PNOC_SLV_BAM_DMA		17
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| #define PNOC_SLV_BLSP_2			18
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| #define PNOC_SLV_USB_HSIC		19
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| #define PNOC_SLV_BLSP_1			20
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| #define PNOC_SLV_USB_HS			21
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| #define PNOC_SLV_PDM			22
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| #define PNOC_SLV_PERIPH_APU_CFG		23
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| #define PNOC_SLV_PNOC_MPU_CFG		24
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| #define PNOC_SLV_PRNG			25
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| #define PNOC_SLV_SERVICE_PNOC		26
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| 
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| #define SNOC_MAS_LPASS_AHB		0
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| #define SNOC_MAS_QDSS_BAM		1
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| #define SNOC_MAS_SNOC_CFG		2
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| #define SNOC_TO_BIMC			3
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| #define SNOC_TO_CNOC			4
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| #define SNOC_TO_PNOC			5
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| #define SNOC_TO_OCMEM_VNOC		6
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| #define SNOC_MAS_CRYPTO_CORE0		7
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| #define SNOC_MAS_CRYPTO_CORE1		8
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| #define SNOC_MAS_LPASS_PROC		9
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| #define SNOC_MAS_MSS			10
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| #define SNOC_MAS_MSS_NAV		11
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| #define SNOC_MAS_OCMEM_DMA		12
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| #define SNOC_MAS_WCSS			13
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| #define SNOC_MAS_QDSS_ETR		14
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| #define SNOC_MAS_USB3			15
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| #define SNOC_SLV_AMPSS			16
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| #define SNOC_SLV_LPASS			17
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| #define SNOC_SLV_USB3			18
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| #define SNOC_SLV_WCSS			19
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| #define SNOC_SLV_OCIMEM			20
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| #define SNOC_SLV_SNOC_OCMEM		21
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| #define SNOC_SLV_SERVICE_SNOC		22
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| #define SNOC_SLV_QDSS_STM		23
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| 
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| #endif
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