forked from mirrors/linux
f366a8dac1
Add a new IOMMU API interface amd_iommu_snp_disable() to transition IOMMU pages to Hypervisor state from Reclaim state after SNP_SHUTDOWN_EX command. Invoke this API from the CCP driver after SNP_SHUTDOWN_EX command. Signed-off-by: Ashish Kalra <ashish.kalra@amd.com> Signed-off-by: Michael Roth <michael.roth@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Link: https://lore.kernel.org/r/20240126041126.1927228-20-michael.roth@amd.com
94 lines
2.1 KiB
C
94 lines
2.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
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* Author: Joerg Roedel <joerg.roedel@amd.com>
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* Leo Duran <leo.duran@amd.com>
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*/
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#ifndef _ASM_X86_AMD_IOMMU_H
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#define _ASM_X86_AMD_IOMMU_H
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#include <linux/types.h>
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struct amd_iommu;
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/*
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* This is mainly used to communicate information back-and-forth
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* between SVM and IOMMU for setting up and tearing down posted
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* interrupt
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*/
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struct amd_iommu_pi_data {
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u32 ga_tag;
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u32 prev_ga_tag;
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u64 base;
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bool is_guest_mode;
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struct vcpu_data *vcpu_data;
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void *ir_data;
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};
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#ifdef CONFIG_AMD_IOMMU
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struct task_struct;
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struct pci_dev;
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extern int amd_iommu_detect(void);
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#else /* CONFIG_AMD_IOMMU */
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static inline int amd_iommu_detect(void) { return -ENODEV; }
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#endif /* CONFIG_AMD_IOMMU */
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#if defined(CONFIG_AMD_IOMMU) && defined(CONFIG_IRQ_REMAP)
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/* IOMMU AVIC Function */
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extern int amd_iommu_register_ga_log_notifier(int (*notifier)(u32));
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extern int
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amd_iommu_update_ga(int cpu, bool is_run, void *data);
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extern int amd_iommu_activate_guest_mode(void *data);
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extern int amd_iommu_deactivate_guest_mode(void *data);
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#else /* defined(CONFIG_AMD_IOMMU) && defined(CONFIG_IRQ_REMAP) */
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static inline int
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amd_iommu_register_ga_log_notifier(int (*notifier)(u32))
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{
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return 0;
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}
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static inline int
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amd_iommu_update_ga(int cpu, bool is_run, void *data)
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{
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return 0;
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}
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static inline int amd_iommu_activate_guest_mode(void *data)
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{
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return 0;
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}
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static inline int amd_iommu_deactivate_guest_mode(void *data)
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{
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return 0;
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}
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#endif /* defined(CONFIG_AMD_IOMMU) && defined(CONFIG_IRQ_REMAP) */
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int amd_iommu_get_num_iommus(void);
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bool amd_iommu_pc_supported(void);
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u8 amd_iommu_pc_get_max_banks(unsigned int idx);
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u8 amd_iommu_pc_get_max_counters(unsigned int idx);
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int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn,
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u64 *value);
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int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn,
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u64 *value);
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struct amd_iommu *get_amd_iommu(unsigned int idx);
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#ifdef CONFIG_KVM_AMD_SEV
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int amd_iommu_snp_disable(void);
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#else
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static inline int amd_iommu_snp_disable(void) { return 0; }
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#endif
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#endif /* _ASM_X86_AMD_IOMMU_H */
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