forked from mirrors/linux
0bbff9ed81
Armv8.9/9.4 PMUv3.9 adds per counter EL0 access controls. Per counter access is enabled with the UEN bit in PMUSERENR_EL1 register. Individual counters are enabled/disabled in the PMUACR_EL1 register. When UEN is set, the CR/ER bits control EL0 write access and must be set to disable write access. With the access controls, the clearing of unused counters can be skipped. KVM also configures PMUSERENR_EL1 in order to trap to EL2. UEN does not need to be set for it since only PMUv3.5 is exposed to guests. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20241002184326.1105499-1-robh@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
318 lines
13 KiB
C
318 lines
13 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2012 ARM Ltd.
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*/
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#ifndef __PERF_ARM_PMUV3_H
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#define __PERF_ARM_PMUV3_H
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#define ARMV8_PMU_MAX_GENERAL_COUNTERS 31
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#define ARMV8_PMU_CYCLE_IDX 31
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#define ARMV8_PMU_INSTR_IDX 32 /* Not accessible from AArch32 */
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/*
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* Common architectural and microarchitectural event numbers.
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*/
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#define ARMV8_PMUV3_PERFCTR_SW_INCR 0x0000
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#define ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL 0x0001
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#define ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL 0x0002
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#define ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL 0x0003
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#define ARMV8_PMUV3_PERFCTR_L1D_CACHE 0x0004
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#define ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL 0x0005
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#define ARMV8_PMUV3_PERFCTR_LD_RETIRED 0x0006
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#define ARMV8_PMUV3_PERFCTR_ST_RETIRED 0x0007
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#define ARMV8_PMUV3_PERFCTR_INST_RETIRED 0x0008
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#define ARMV8_PMUV3_PERFCTR_EXC_TAKEN 0x0009
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#define ARMV8_PMUV3_PERFCTR_EXC_RETURN 0x000A
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#define ARMV8_PMUV3_PERFCTR_CID_WRITE_RETIRED 0x000B
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#define ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED 0x000C
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#define ARMV8_PMUV3_PERFCTR_BR_IMMED_RETIRED 0x000D
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#define ARMV8_PMUV3_PERFCTR_BR_RETURN_RETIRED 0x000E
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#define ARMV8_PMUV3_PERFCTR_UNALIGNED_LDST_RETIRED 0x000F
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#define ARMV8_PMUV3_PERFCTR_BR_MIS_PRED 0x0010
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#define ARMV8_PMUV3_PERFCTR_CPU_CYCLES 0x0011
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#define ARMV8_PMUV3_PERFCTR_BR_PRED 0x0012
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#define ARMV8_PMUV3_PERFCTR_MEM_ACCESS 0x0013
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#define ARMV8_PMUV3_PERFCTR_L1I_CACHE 0x0014
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#define ARMV8_PMUV3_PERFCTR_L1D_CACHE_WB 0x0015
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#define ARMV8_PMUV3_PERFCTR_L2D_CACHE 0x0016
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#define ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL 0x0017
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#define ARMV8_PMUV3_PERFCTR_L2D_CACHE_WB 0x0018
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#define ARMV8_PMUV3_PERFCTR_BUS_ACCESS 0x0019
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#define ARMV8_PMUV3_PERFCTR_MEMORY_ERROR 0x001A
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#define ARMV8_PMUV3_PERFCTR_INST_SPEC 0x001B
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#define ARMV8_PMUV3_PERFCTR_TTBR_WRITE_RETIRED 0x001C
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#define ARMV8_PMUV3_PERFCTR_BUS_CYCLES 0x001D
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#define ARMV8_PMUV3_PERFCTR_CHAIN 0x001E
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#define ARMV8_PMUV3_PERFCTR_L1D_CACHE_ALLOCATE 0x001F
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#define ARMV8_PMUV3_PERFCTR_L2D_CACHE_ALLOCATE 0x0020
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#define ARMV8_PMUV3_PERFCTR_BR_RETIRED 0x0021
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#define ARMV8_PMUV3_PERFCTR_BR_MIS_PRED_RETIRED 0x0022
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#define ARMV8_PMUV3_PERFCTR_STALL_FRONTEND 0x0023
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#define ARMV8_PMUV3_PERFCTR_STALL_BACKEND 0x0024
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#define ARMV8_PMUV3_PERFCTR_L1D_TLB 0x0025
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#define ARMV8_PMUV3_PERFCTR_L1I_TLB 0x0026
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#define ARMV8_PMUV3_PERFCTR_L2I_CACHE 0x0027
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#define ARMV8_PMUV3_PERFCTR_L2I_CACHE_REFILL 0x0028
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#define ARMV8_PMUV3_PERFCTR_L3D_CACHE_ALLOCATE 0x0029
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#define ARMV8_PMUV3_PERFCTR_L3D_CACHE_REFILL 0x002A
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#define ARMV8_PMUV3_PERFCTR_L3D_CACHE 0x002B
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#define ARMV8_PMUV3_PERFCTR_L3D_CACHE_WB 0x002C
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#define ARMV8_PMUV3_PERFCTR_L2D_TLB_REFILL 0x002D
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#define ARMV8_PMUV3_PERFCTR_L2I_TLB_REFILL 0x002E
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#define ARMV8_PMUV3_PERFCTR_L2D_TLB 0x002F
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#define ARMV8_PMUV3_PERFCTR_L2I_TLB 0x0030
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#define ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS 0x0031
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#define ARMV8_PMUV3_PERFCTR_LL_CACHE 0x0032
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#define ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS 0x0033
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#define ARMV8_PMUV3_PERFCTR_DTLB_WALK 0x0034
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#define ARMV8_PMUV3_PERFCTR_ITLB_WALK 0x0035
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#define ARMV8_PMUV3_PERFCTR_LL_CACHE_RD 0x0036
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#define ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD 0x0037
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#define ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS_RD 0x0038
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#define ARMV8_PMUV3_PERFCTR_L1D_CACHE_LMISS_RD 0x0039
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#define ARMV8_PMUV3_PERFCTR_OP_RETIRED 0x003A
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#define ARMV8_PMUV3_PERFCTR_OP_SPEC 0x003B
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#define ARMV8_PMUV3_PERFCTR_STALL 0x003C
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#define ARMV8_PMUV3_PERFCTR_STALL_SLOT_BACKEND 0x003D
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#define ARMV8_PMUV3_PERFCTR_STALL_SLOT_FRONTEND 0x003E
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#define ARMV8_PMUV3_PERFCTR_STALL_SLOT 0x003F
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/* Statistical profiling extension microarchitectural events */
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#define ARMV8_SPE_PERFCTR_SAMPLE_POP 0x4000
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#define ARMV8_SPE_PERFCTR_SAMPLE_FEED 0x4001
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#define ARMV8_SPE_PERFCTR_SAMPLE_FILTRATE 0x4002
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#define ARMV8_SPE_PERFCTR_SAMPLE_COLLISION 0x4003
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/* AMUv1 architecture events */
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#define ARMV8_AMU_PERFCTR_CNT_CYCLES 0x4004
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#define ARMV8_AMU_PERFCTR_STALL_BACKEND_MEM 0x4005
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/* long-latency read miss events */
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#define ARMV8_PMUV3_PERFCTR_L1I_CACHE_LMISS 0x4006
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#define ARMV8_PMUV3_PERFCTR_L2D_CACHE_LMISS_RD 0x4009
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#define ARMV8_PMUV3_PERFCTR_L2I_CACHE_LMISS 0x400A
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#define ARMV8_PMUV3_PERFCTR_L3D_CACHE_LMISS_RD 0x400B
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/* Trace buffer events */
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#define ARMV8_PMUV3_PERFCTR_TRB_WRAP 0x400C
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#define ARMV8_PMUV3_PERFCTR_TRB_TRIG 0x400E
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/* Trace unit events */
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#define ARMV8_PMUV3_PERFCTR_TRCEXTOUT0 0x4010
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#define ARMV8_PMUV3_PERFCTR_TRCEXTOUT1 0x4011
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#define ARMV8_PMUV3_PERFCTR_TRCEXTOUT2 0x4012
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#define ARMV8_PMUV3_PERFCTR_TRCEXTOUT3 0x4013
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#define ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT4 0x4018
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#define ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT5 0x4019
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#define ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT6 0x401A
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#define ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT7 0x401B
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/* additional latency from alignment events */
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#define ARMV8_PMUV3_PERFCTR_LDST_ALIGN_LAT 0x4020
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#define ARMV8_PMUV3_PERFCTR_LD_ALIGN_LAT 0x4021
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#define ARMV8_PMUV3_PERFCTR_ST_ALIGN_LAT 0x4022
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/* Armv8.5 Memory Tagging Extension events */
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#define ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED 0x4024
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#define ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_RD 0x4025
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#define ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_WR 0x4026
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/* ARMv8 recommended implementation defined event types */
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#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD 0x0040
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#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR 0x0041
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#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD 0x0042
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#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR 0x0043
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#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_INNER 0x0044
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#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_OUTER 0x0045
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#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WB_VICTIM 0x0046
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#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WB_CLEAN 0x0047
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#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_INVAL 0x0048
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#define ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD 0x004C
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#define ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR 0x004D
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#define ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD 0x004E
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#define ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR 0x004F
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#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_RD 0x0050
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#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WR 0x0051
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#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_REFILL_RD 0x0052
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#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_REFILL_WR 0x0053
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#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WB_VICTIM 0x0056
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#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WB_CLEAN 0x0057
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#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_INVAL 0x0058
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#define ARMV8_IMPDEF_PERFCTR_L2D_TLB_REFILL_RD 0x005C
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#define ARMV8_IMPDEF_PERFCTR_L2D_TLB_REFILL_WR 0x005D
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#define ARMV8_IMPDEF_PERFCTR_L2D_TLB_RD 0x005E
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#define ARMV8_IMPDEF_PERFCTR_L2D_TLB_WR 0x005F
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#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD 0x0060
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#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR 0x0061
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#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_SHARED 0x0062
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#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_NOT_SHARED 0x0063
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#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_NORMAL 0x0064
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#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_PERIPH 0x0065
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#define ARMV8_IMPDEF_PERFCTR_MEM_ACCESS_RD 0x0066
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#define ARMV8_IMPDEF_PERFCTR_MEM_ACCESS_WR 0x0067
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#define ARMV8_IMPDEF_PERFCTR_UNALIGNED_LD_SPEC 0x0068
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#define ARMV8_IMPDEF_PERFCTR_UNALIGNED_ST_SPEC 0x0069
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#define ARMV8_IMPDEF_PERFCTR_UNALIGNED_LDST_SPEC 0x006A
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#define ARMV8_IMPDEF_PERFCTR_LDREX_SPEC 0x006C
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#define ARMV8_IMPDEF_PERFCTR_STREX_PASS_SPEC 0x006D
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#define ARMV8_IMPDEF_PERFCTR_STREX_FAIL_SPEC 0x006E
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#define ARMV8_IMPDEF_PERFCTR_STREX_SPEC 0x006F
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#define ARMV8_IMPDEF_PERFCTR_LD_SPEC 0x0070
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#define ARMV8_IMPDEF_PERFCTR_ST_SPEC 0x0071
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#define ARMV8_IMPDEF_PERFCTR_LDST_SPEC 0x0072
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#define ARMV8_IMPDEF_PERFCTR_DP_SPEC 0x0073
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#define ARMV8_IMPDEF_PERFCTR_ASE_SPEC 0x0074
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#define ARMV8_IMPDEF_PERFCTR_VFP_SPEC 0x0075
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#define ARMV8_IMPDEF_PERFCTR_PC_WRITE_SPEC 0x0076
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#define ARMV8_IMPDEF_PERFCTR_CRYPTO_SPEC 0x0077
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#define ARMV8_IMPDEF_PERFCTR_BR_IMMED_SPEC 0x0078
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#define ARMV8_IMPDEF_PERFCTR_BR_RETURN_SPEC 0x0079
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#define ARMV8_IMPDEF_PERFCTR_BR_INDIRECT_SPEC 0x007A
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#define ARMV8_IMPDEF_PERFCTR_ISB_SPEC 0x007C
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#define ARMV8_IMPDEF_PERFCTR_DSB_SPEC 0x007D
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#define ARMV8_IMPDEF_PERFCTR_DMB_SPEC 0x007E
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#define ARMV8_IMPDEF_PERFCTR_EXC_UNDEF 0x0081
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#define ARMV8_IMPDEF_PERFCTR_EXC_SVC 0x0082
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#define ARMV8_IMPDEF_PERFCTR_EXC_PABORT 0x0083
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#define ARMV8_IMPDEF_PERFCTR_EXC_DABORT 0x0084
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#define ARMV8_IMPDEF_PERFCTR_EXC_IRQ 0x0086
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#define ARMV8_IMPDEF_PERFCTR_EXC_FIQ 0x0087
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#define ARMV8_IMPDEF_PERFCTR_EXC_SMC 0x0088
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#define ARMV8_IMPDEF_PERFCTR_EXC_HVC 0x008A
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#define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_PABORT 0x008B
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#define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_DABORT 0x008C
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#define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_OTHER 0x008D
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#define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_IRQ 0x008E
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#define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_FIQ 0x008F
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#define ARMV8_IMPDEF_PERFCTR_RC_LD_SPEC 0x0090
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#define ARMV8_IMPDEF_PERFCTR_RC_ST_SPEC 0x0091
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#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_RD 0x00A0
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#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WR 0x00A1
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#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_REFILL_RD 0x00A2
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#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_REFILL_WR 0x00A3
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#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WB_VICTIM 0x00A6
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#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WB_CLEAN 0x00A7
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#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_INVAL 0x00A8
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/*
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* Per-CPU PMCR: config reg
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*/
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#define ARMV8_PMU_PMCR_E (1 << 0) /* Enable all counters */
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#define ARMV8_PMU_PMCR_P (1 << 1) /* Reset all counters */
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#define ARMV8_PMU_PMCR_C (1 << 2) /* Cycle counter reset */
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#define ARMV8_PMU_PMCR_D (1 << 3) /* CCNT counts every 64th cpu cycle */
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#define ARMV8_PMU_PMCR_X (1 << 4) /* Export to ETM */
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#define ARMV8_PMU_PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/
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#define ARMV8_PMU_PMCR_LC (1 << 6) /* Overflow on 64 bit cycle counter */
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#define ARMV8_PMU_PMCR_LP (1 << 7) /* Long event counter enable */
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#define ARMV8_PMU_PMCR_N GENMASK(15, 11) /* Number of counters supported */
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/* Mask for writable bits */
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#define ARMV8_PMU_PMCR_MASK (ARMV8_PMU_PMCR_E | ARMV8_PMU_PMCR_P | \
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ARMV8_PMU_PMCR_C | ARMV8_PMU_PMCR_D | \
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ARMV8_PMU_PMCR_X | ARMV8_PMU_PMCR_DP | \
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ARMV8_PMU_PMCR_LC | ARMV8_PMU_PMCR_LP)
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/*
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* PMOVSR: counters overflow flag status reg
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*/
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#define ARMV8_PMU_OVSR_P GENMASK(30, 0)
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#define ARMV8_PMU_OVSR_C BIT(31)
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#define ARMV8_PMU_OVSR_F BIT_ULL(32) /* arm64 only */
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/* Mask for writable bits is both P and C fields */
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#define ARMV8_PMU_OVERFLOWED_MASK (ARMV8_PMU_OVSR_P | ARMV8_PMU_OVSR_C | \
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ARMV8_PMU_OVSR_F)
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/*
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* PMXEVTYPER: Event selection reg
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*/
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#define ARMV8_PMU_EVTYPE_EVENT GENMASK(15, 0) /* Mask for EVENT bits */
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#define ARMV8_PMU_EVTYPE_TH GENMASK_ULL(43, 32) /* arm64 only */
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#define ARMV8_PMU_EVTYPE_TC GENMASK_ULL(63, 61) /* arm64 only */
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/*
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* Event filters for PMUv3
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*/
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#define ARMV8_PMU_EXCLUDE_EL1 (1U << 31)
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#define ARMV8_PMU_EXCLUDE_EL0 (1U << 30)
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#define ARMV8_PMU_EXCLUDE_NS_EL1 (1U << 29)
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#define ARMV8_PMU_EXCLUDE_NS_EL0 (1U << 28)
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#define ARMV8_PMU_INCLUDE_EL2 (1U << 27)
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#define ARMV8_PMU_EXCLUDE_EL3 (1U << 26)
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/*
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* PMUSERENR: user enable reg
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*/
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#define ARMV8_PMU_USERENR_EN (1 << 0) /* PMU regs can be accessed at EL0 */
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#define ARMV8_PMU_USERENR_SW (1 << 1) /* PMSWINC can be written at EL0 */
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#define ARMV8_PMU_USERENR_CR (1 << 2) /* Cycle counter can be read at EL0 */
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#define ARMV8_PMU_USERENR_ER (1 << 3) /* Event counter can be read at EL0 */
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#define ARMV8_PMU_USERENR_UEN (1 << 4) /* Fine grained per counter access at EL0 */
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/* Mask for writable bits */
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#define ARMV8_PMU_USERENR_MASK (ARMV8_PMU_USERENR_EN | ARMV8_PMU_USERENR_SW | \
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ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_ER)
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/* PMMIR_EL1.SLOTS mask */
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#define ARMV8_PMU_SLOTS GENMASK(7, 0)
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#define ARMV8_PMU_BUS_SLOTS GENMASK(15, 8)
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#define ARMV8_PMU_BUS_WIDTH GENMASK(19, 16)
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#define ARMV8_PMU_THWIDTH GENMASK(23, 20)
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/*
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* This code is really good
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*/
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#define PMEVN_CASE(n, case_macro) \
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case n: case_macro(n); break
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#define PMEVN_SWITCH(x, case_macro) \
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do { \
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switch (x) { \
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PMEVN_CASE(0, case_macro); \
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PMEVN_CASE(1, case_macro); \
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PMEVN_CASE(2, case_macro); \
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PMEVN_CASE(3, case_macro); \
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PMEVN_CASE(4, case_macro); \
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PMEVN_CASE(5, case_macro); \
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PMEVN_CASE(6, case_macro); \
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PMEVN_CASE(7, case_macro); \
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PMEVN_CASE(8, case_macro); \
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PMEVN_CASE(9, case_macro); \
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PMEVN_CASE(10, case_macro); \
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PMEVN_CASE(11, case_macro); \
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PMEVN_CASE(12, case_macro); \
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PMEVN_CASE(13, case_macro); \
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PMEVN_CASE(14, case_macro); \
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PMEVN_CASE(15, case_macro); \
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PMEVN_CASE(16, case_macro); \
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PMEVN_CASE(17, case_macro); \
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PMEVN_CASE(18, case_macro); \
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PMEVN_CASE(19, case_macro); \
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PMEVN_CASE(20, case_macro); \
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PMEVN_CASE(21, case_macro); \
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PMEVN_CASE(22, case_macro); \
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PMEVN_CASE(23, case_macro); \
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PMEVN_CASE(24, case_macro); \
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PMEVN_CASE(25, case_macro); \
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PMEVN_CASE(26, case_macro); \
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PMEVN_CASE(27, case_macro); \
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PMEVN_CASE(28, case_macro); \
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PMEVN_CASE(29, case_macro); \
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PMEVN_CASE(30, case_macro); \
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default: WARN(1, "Invalid PMEV* index\n"); \
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} \
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|
} while (0)
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|
|
|
#include <asm/arm_pmuv3.h>
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|
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#endif
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