forked from mirrors/linux
d2912cb15b
Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
217 lines
7.4 KiB
C
217 lines
7.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* include/linux/amba/pl080.h
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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* http://armlinux.simtec.co.uk/
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* Ben Dooks <ben@simtec.co.uk>
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*
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* ARM PrimeCell PL080 DMA controller
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*/
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/* Note, there are some Samsung updates to this controller block which
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* make it not entierly compatible with the PL080 specification from
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* ARM. When in doubt, check the Samsung documentation first.
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*
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* The Samsung defines are PL080S, and add an extra control register,
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* the ability to move more than 2^11 counts of data and some extra
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* OneNAND features.
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*/
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#ifndef ASM_PL080_H
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#define ASM_PL080_H
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#define PL080_INT_STATUS (0x00)
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#define PL080_TC_STATUS (0x04)
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#define PL080_TC_CLEAR (0x08)
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#define PL080_ERR_STATUS (0x0C)
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#define PL080_ERR_CLEAR (0x10)
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#define PL080_RAW_TC_STATUS (0x14)
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#define PL080_RAW_ERR_STATUS (0x18)
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#define PL080_EN_CHAN (0x1c)
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#define PL080_SOFT_BREQ (0x20)
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#define PL080_SOFT_SREQ (0x24)
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#define PL080_SOFT_LBREQ (0x28)
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#define PL080_SOFT_LSREQ (0x2C)
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#define PL080_CONFIG (0x30)
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#define PL080_CONFIG_M2_BE BIT(2)
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#define PL080_CONFIG_M1_BE BIT(1)
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#define PL080_CONFIG_ENABLE BIT(0)
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#define PL080_SYNC (0x34)
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/* The Faraday Technology FTDMAC020 variant registers */
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#define FTDMAC020_CH_BUSY (0x20)
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/* Identical to PL080_CONFIG */
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#define FTDMAC020_CSR (0x24)
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/* Identical to PL080_SYNC */
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#define FTDMAC020_SYNC (0x2C)
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#define FTDMAC020_REVISION (0x30)
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#define FTDMAC020_FEATURE (0x34)
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/* Per channel configuration registers */
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#define PL080_Cx_BASE(x) ((0x100 + (x * 0x20)))
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#define PL080_CH_SRC_ADDR (0x00)
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#define PL080_CH_DST_ADDR (0x04)
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#define PL080_CH_LLI (0x08)
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#define PL080_CH_CONTROL (0x0C)
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#define PL080_CH_CONFIG (0x10)
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#define PL080S_CH_CONTROL2 (0x10)
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#define PL080S_CH_CONFIG (0x14)
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/* The Faraday FTDMAC020 derivative shuffles the registers around */
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#define FTDMAC020_CH_CSR (0x00)
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#define FTDMAC020_CH_CFG (0x04)
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#define FTDMAC020_CH_SRC_ADDR (0x08)
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#define FTDMAC020_CH_DST_ADDR (0x0C)
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#define FTDMAC020_CH_LLP (0x10)
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#define FTDMAC020_CH_SIZE (0x14)
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#define PL080_LLI_ADDR_MASK GENMASK(31, 2)
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#define PL080_LLI_ADDR_SHIFT (2)
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#define PL080_LLI_LM_AHB2 BIT(0)
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#define PL080_CONTROL_TC_IRQ_EN BIT(31)
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#define PL080_CONTROL_PROT_MASK GENMASK(30, 28)
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#define PL080_CONTROL_PROT_SHIFT (28)
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#define PL080_CONTROL_PROT_CACHE BIT(30)
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#define PL080_CONTROL_PROT_BUFF BIT(29)
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#define PL080_CONTROL_PROT_SYS BIT(28)
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#define PL080_CONTROL_DST_INCR BIT(27)
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#define PL080_CONTROL_SRC_INCR BIT(26)
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#define PL080_CONTROL_DST_AHB2 BIT(25)
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#define PL080_CONTROL_SRC_AHB2 BIT(24)
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#define PL080_CONTROL_DWIDTH_MASK GENMASK(23, 21)
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#define PL080_CONTROL_DWIDTH_SHIFT (21)
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#define PL080_CONTROL_SWIDTH_MASK GENMASK(20, 18)
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#define PL080_CONTROL_SWIDTH_SHIFT (18)
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#define PL080_CONTROL_DB_SIZE_MASK GENMASK(17, 15)
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#define PL080_CONTROL_DB_SIZE_SHIFT (15)
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#define PL080_CONTROL_SB_SIZE_MASK GENMASK(14, 12)
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#define PL080_CONTROL_SB_SIZE_SHIFT (12)
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#define PL080_CONTROL_TRANSFER_SIZE_MASK GENMASK(11, 0)
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#define PL080S_CONTROL_TRANSFER_SIZE_MASK GENMASK(24, 0)
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#define PL080_CONTROL_TRANSFER_SIZE_SHIFT (0)
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#define PL080_BSIZE_1 (0x0)
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#define PL080_BSIZE_4 (0x1)
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#define PL080_BSIZE_8 (0x2)
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#define PL080_BSIZE_16 (0x3)
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#define PL080_BSIZE_32 (0x4)
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#define PL080_BSIZE_64 (0x5)
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#define PL080_BSIZE_128 (0x6)
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#define PL080_BSIZE_256 (0x7)
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#define PL080_WIDTH_8BIT (0x0)
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#define PL080_WIDTH_16BIT (0x1)
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#define PL080_WIDTH_32BIT (0x2)
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#define PL080N_CONFIG_ITPROT BIT(20)
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#define PL080N_CONFIG_SECPROT BIT(19)
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#define PL080_CONFIG_HALT BIT(18)
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#define PL080_CONFIG_ACTIVE BIT(17) /* RO */
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#define PL080_CONFIG_LOCK BIT(16)
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#define PL080_CONFIG_TC_IRQ_MASK BIT(15)
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#define PL080_CONFIG_ERR_IRQ_MASK BIT(14)
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#define PL080_CONFIG_FLOW_CONTROL_MASK GENMASK(13, 11)
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#define PL080_CONFIG_FLOW_CONTROL_SHIFT (11)
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#define PL080_CONFIG_DST_SEL_MASK GENMASK(9, 6)
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#define PL080_CONFIG_DST_SEL_SHIFT (6)
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#define PL080_CONFIG_SRC_SEL_MASK GENMASK(4, 1)
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#define PL080_CONFIG_SRC_SEL_SHIFT (1)
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#define PL080_CONFIG_ENABLE BIT(0)
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#define PL080_FLOW_MEM2MEM (0x0)
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#define PL080_FLOW_MEM2PER (0x1)
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#define PL080_FLOW_PER2MEM (0x2)
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#define PL080_FLOW_SRC2DST (0x3)
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#define PL080_FLOW_SRC2DST_DST (0x4)
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#define PL080_FLOW_MEM2PER_PER (0x5)
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#define PL080_FLOW_PER2MEM_PER (0x6)
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#define PL080_FLOW_SRC2DST_SRC (0x7)
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#define FTDMAC020_CH_CSR_TC_MSK BIT(31)
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/* Later versions have a threshold in bits 24..26, */
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#define FTDMAC020_CH_CSR_FIFOTH_MSK GENMASK(26, 24)
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#define FTDMAC020_CH_CSR_FIFOTH_SHIFT (24)
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#define FTDMAC020_CH_CSR_CHPR1_MSK GENMASK(23, 22)
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#define FTDMAC020_CH_CSR_PROT3 BIT(21)
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#define FTDMAC020_CH_CSR_PROT2 BIT(20)
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#define FTDMAC020_CH_CSR_PROT1 BIT(19)
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#define FTDMAC020_CH_CSR_SRC_SIZE_MSK GENMASK(18, 16)
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#define FTDMAC020_CH_CSR_SRC_SIZE_SHIFT (16)
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#define FTDMAC020_CH_CSR_ABT BIT(15)
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#define FTDMAC020_CH_CSR_SRC_WIDTH_MSK GENMASK(13, 11)
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#define FTDMAC020_CH_CSR_SRC_WIDTH_SHIFT (11)
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#define FTDMAC020_CH_CSR_DST_WIDTH_MSK GENMASK(10, 8)
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#define FTDMAC020_CH_CSR_DST_WIDTH_SHIFT (8)
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#define FTDMAC020_CH_CSR_MODE BIT(7)
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/* 00 = increase, 01 = decrease, 10 = fix */
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#define FTDMAC020_CH_CSR_SRCAD_CTL_MSK GENMASK(6, 5)
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#define FTDMAC020_CH_CSR_SRCAD_CTL_SHIFT (5)
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#define FTDMAC020_CH_CSR_DSTAD_CTL_MSK GENMASK(4, 3)
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#define FTDMAC020_CH_CSR_DSTAD_CTL_SHIFT (3)
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#define FTDMAC020_CH_CSR_SRC_SEL BIT(2)
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#define FTDMAC020_CH_CSR_DST_SEL BIT(1)
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#define FTDMAC020_CH_CSR_EN BIT(0)
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/* FIFO threshold setting */
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#define FTDMAC020_CH_CSR_FIFOTH_1 (0x0)
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#define FTDMAC020_CH_CSR_FIFOTH_2 (0x1)
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#define FTDMAC020_CH_CSR_FIFOTH_4 (0x2)
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#define FTDMAC020_CH_CSR_FIFOTH_8 (0x3)
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#define FTDMAC020_CH_CSR_FIFOTH_16 (0x4)
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/* The FTDMAC020 supports 64bit wide transfers */
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#define FTDMAC020_WIDTH_64BIT (0x3)
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/* Address can be increased, decreased or fixed */
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#define FTDMAC020_CH_CSR_SRCAD_CTL_INC (0x0)
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#define FTDMAC020_CH_CSR_SRCAD_CTL_DEC (0x1)
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#define FTDMAC020_CH_CSR_SRCAD_CTL_FIXED (0x2)
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#define FTDMAC020_CH_CFG_LLP_CNT_MASK GENMASK(19, 16)
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#define FTDMAC020_CH_CFG_LLP_CNT_SHIFT (16)
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#define FTDMAC020_CH_CFG_BUSY BIT(8)
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#define FTDMAC020_CH_CFG_INT_ABT_MASK BIT(2)
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#define FTDMAC020_CH_CFG_INT_ERR_MASK BIT(1)
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#define FTDMAC020_CH_CFG_INT_TC_MASK BIT(0)
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/* Inside the LLIs, the applicable CSR fields are mapped differently */
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#define FTDMAC020_LLI_TC_MSK BIT(28)
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#define FTDMAC020_LLI_SRC_WIDTH_MSK GENMASK(27, 25)
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#define FTDMAC020_LLI_SRC_WIDTH_SHIFT (25)
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#define FTDMAC020_LLI_DST_WIDTH_MSK GENMASK(24, 22)
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#define FTDMAC020_LLI_DST_WIDTH_SHIFT (22)
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#define FTDMAC020_LLI_SRCAD_CTL_MSK GENMASK(21, 20)
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#define FTDMAC020_LLI_SRCAD_CTL_SHIFT (20)
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#define FTDMAC020_LLI_DSTAD_CTL_MSK GENMASK(19, 18)
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#define FTDMAC020_LLI_DSTAD_CTL_SHIFT (18)
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#define FTDMAC020_LLI_SRC_SEL BIT(17)
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#define FTDMAC020_LLI_DST_SEL BIT(16)
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#define FTDMAC020_LLI_TRANSFER_SIZE_MASK GENMASK(11, 0)
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#define FTDMAC020_LLI_TRANSFER_SIZE_SHIFT (0)
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#define FTDMAC020_CFG_LLP_CNT_MASK GENMASK(19, 16)
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#define FTDMAC020_CFG_LLP_CNT_SHIFT (16)
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#define FTDMAC020_CFG_BUSY BIT(8)
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#define FTDMAC020_CFG_INT_ABT_MSK BIT(2)
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#define FTDMAC020_CFG_INT_ERR_MSK BIT(1)
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#define FTDMAC020_CFG_INT_TC_MSK BIT(0)
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/* DMA linked list chain structure */
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struct pl080_lli {
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u32 src_addr;
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u32 dst_addr;
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u32 next_lli;
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u32 control0;
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};
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struct pl080s_lli {
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u32 src_addr;
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u32 dst_addr;
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u32 next_lli;
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u32 control0;
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u32 control1;
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};
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#endif /* ASM_PL080_H */
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