forked from mirrors/linux
1f78c56007
The driver uses bit shifts and hexadecimal expressions to declare constants. Replace that with the BIT(), GENMASK() & FIELD_PREP_CONST() macros to clarify intent. include/linux/amba/serial.h gets included from arch/arm/include/debug/pl01x.S. Avoid includes and macro tricks for the four defines that are involved: UART01x_DR, UART01x_FR, UART01x_FR_TXFF and UART01x_FR_BUSY. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com> Link: https://lore.kernel.org/r/20231207-mbly-uart-v6-1-e384afa5e78c@bootlin.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
237 lines
10 KiB
C
237 lines
10 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* linux/include/asm-arm/hardware/serial_amba.h
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*
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* Internal header file for AMBA serial ports
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*
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* Copyright (C) ARM Limited
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* Copyright (C) 2000 Deep Blue Solutions Ltd.
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*/
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#ifndef ASM_ARM_HARDWARE_SERIAL_AMBA_H
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#define ASM_ARM_HARDWARE_SERIAL_AMBA_H
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#ifndef __ASSEMBLY__
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#include <linux/bitfield.h>
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#include <linux/bits.h>
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#endif
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#include <linux/types.h>
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/* -------------------------------------------------------------------------------
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* From AMBA UART (PL010) Block Specification
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* -------------------------------------------------------------------------------
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* UART Register Offsets.
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*/
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#define UART01x_DR 0x00 /* Data read or written from the interface. */
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#define UART01x_RSR 0x04 /* Receive status register (Read). */
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#define UART01x_ECR 0x04 /* Error clear register (Write). */
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#define UART010_LCRH 0x08 /* Line control register, high byte. */
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#define ST_UART011_DMAWM 0x08 /* DMA watermark configure register. */
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#define UART010_LCRM 0x0C /* Line control register, middle byte. */
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#define ST_UART011_TIMEOUT 0x0C /* Timeout period register. */
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#define UART010_LCRL 0x10 /* Line control register, low byte. */
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#define UART010_CR 0x14 /* Control register. */
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#define UART01x_FR 0x18 /* Flag register (Read only). */
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#define UART010_IIR 0x1C /* Interrupt identification register (Read). */
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#define UART010_ICR 0x1C /* Interrupt clear register (Write). */
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#define ST_UART011_LCRH_RX 0x1C /* Rx line control register. */
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#define UART01x_ILPR 0x20 /* IrDA low power counter register. */
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#define UART011_IBRD 0x24 /* Integer baud rate divisor register. */
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#define UART011_FBRD 0x28 /* Fractional baud rate divisor register. */
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#define UART011_LCRH 0x2c /* Line control register. */
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#define ST_UART011_LCRH_TX 0x2c /* Tx Line control register. */
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#define UART011_CR 0x30 /* Control register. */
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#define UART011_IFLS 0x34 /* Interrupt fifo level select. */
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#define UART011_IMSC 0x38 /* Interrupt mask. */
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#define UART011_RIS 0x3c /* Raw interrupt status. */
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#define UART011_MIS 0x40 /* Masked interrupt status. */
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#define UART011_ICR 0x44 /* Interrupt clear register. */
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#define UART011_DMACR 0x48 /* DMA control register. */
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#define ST_UART011_XFCR 0x50 /* XON/XOFF control register. */
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#define ST_UART011_XON1 0x54 /* XON1 register. */
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#define ST_UART011_XON2 0x58 /* XON2 register. */
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#define ST_UART011_XOFF1 0x5C /* XON1 register. */
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#define ST_UART011_XOFF2 0x60 /* XON2 register. */
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#define ST_UART011_ITCR 0x80 /* Integration test control register. */
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#define ST_UART011_ITIP 0x84 /* Integration test input register. */
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#define ST_UART011_ABCR 0x100 /* Autobaud control register. */
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#define ST_UART011_ABIMSC 0x15C /* Autobaud interrupt mask/clear register. */
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/*
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* ZTE UART register offsets. This UART has a radically different address
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* allocation from the ARM and ST variants, so we list all registers here.
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* We assume unlisted registers do not exist.
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*/
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#define ZX_UART011_DR 0x04
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#define ZX_UART011_FR 0x14
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#define ZX_UART011_IBRD 0x24
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#define ZX_UART011_FBRD 0x28
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#define ZX_UART011_LCRH 0x30
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#define ZX_UART011_CR 0x34
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#define ZX_UART011_IFLS 0x38
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#define ZX_UART011_IMSC 0x40
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#define ZX_UART011_RIS 0x44
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#define ZX_UART011_MIS 0x48
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#define ZX_UART011_ICR 0x4c
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#define ZX_UART011_DMACR 0x50
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#define UART011_DR_OE BIT(11)
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#define UART011_DR_BE BIT(10)
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#define UART011_DR_PE BIT(9)
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#define UART011_DR_FE BIT(8)
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#define UART01x_RSR_OE BIT(3)
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#define UART01x_RSR_BE BIT(2)
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#define UART01x_RSR_PE BIT(1)
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#define UART01x_RSR_FE BIT(0)
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#define UART011_FR_RI BIT(8)
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#define UART011_FR_TXFE BIT(7)
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#define UART011_FR_RXFF BIT(6)
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#define UART01x_FR_TXFF (1 << 5) /* used in ASM */
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#define UART01x_FR_RXFE BIT(4)
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#define UART01x_FR_BUSY (1 << 3) /* used in ASM */
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#define UART01x_FR_DCD BIT(2)
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#define UART01x_FR_DSR BIT(1)
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#define UART01x_FR_CTS BIT(0)
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#define UART01x_FR_TMSK (UART01x_FR_TXFF + UART01x_FR_BUSY)
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/*
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* Some bits of Flag Register on ZTE device have different position from
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* standard ones.
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*/
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#define ZX_UART01x_FR_BUSY BIT(8)
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#define ZX_UART01x_FR_DSR BIT(3)
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#define ZX_UART01x_FR_CTS BIT(1)
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#define ZX_UART011_FR_RI BIT(0)
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#define UART011_CR_CTSEN BIT(15) /* CTS hardware flow control */
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#define UART011_CR_RTSEN BIT(14) /* RTS hardware flow control */
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#define UART011_CR_OUT2 BIT(13) /* OUT2 */
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#define UART011_CR_OUT1 BIT(12) /* OUT1 */
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#define UART011_CR_RTS BIT(11) /* RTS */
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#define UART011_CR_DTR BIT(10) /* DTR */
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#define UART011_CR_RXE BIT(9) /* receive enable */
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#define UART011_CR_TXE BIT(8) /* transmit enable */
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#define UART011_CR_LBE BIT(7) /* loopback enable */
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#define UART010_CR_RTIE BIT(6)
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#define UART010_CR_TIE BIT(5)
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#define UART010_CR_RIE BIT(4)
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#define UART010_CR_MSIE BIT(3)
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#define ST_UART011_CR_OVSFACT BIT(3) /* Oversampling factor */
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#define UART01x_CR_IIRLP BIT(2) /* SIR low power mode */
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#define UART01x_CR_SIREN BIT(1) /* SIR enable */
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#define UART01x_CR_UARTEN BIT(0) /* UART enable */
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#define UART011_LCRH_SPS BIT(7)
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#define UART01x_LCRH_WLEN_8 0x60
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#define UART01x_LCRH_WLEN_7 0x40
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#define UART01x_LCRH_WLEN_6 0x20
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#define UART01x_LCRH_WLEN_5 0x00
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#define UART01x_LCRH_FEN BIT(4)
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#define UART01x_LCRH_STP2 BIT(3)
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#define UART01x_LCRH_EPS BIT(2)
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#define UART01x_LCRH_PEN BIT(1)
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#define UART01x_LCRH_BRK BIT(0)
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#define ST_UART011_DMAWM_RX GENMASK(5, 3)
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#define ST_UART011_DMAWM_RX_1 FIELD_PREP_CONST(ST_UART011_DMAWM_RX, 0)
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#define ST_UART011_DMAWM_RX_2 FIELD_PREP_CONST(ST_UART011_DMAWM_RX, 1)
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#define ST_UART011_DMAWM_RX_4 FIELD_PREP_CONST(ST_UART011_DMAWM_RX, 2)
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#define ST_UART011_DMAWM_RX_8 FIELD_PREP_CONST(ST_UART011_DMAWM_RX, 3)
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#define ST_UART011_DMAWM_RX_16 FIELD_PREP_CONST(ST_UART011_DMAWM_RX, 4)
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#define ST_UART011_DMAWM_RX_32 FIELD_PREP_CONST(ST_UART011_DMAWM_RX, 5)
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#define ST_UART011_DMAWM_RX_48 FIELD_PREP_CONST(ST_UART011_DMAWM_RX, 6)
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#define ST_UART011_DMAWM_TX GENMASK(2, 0)
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#define ST_UART011_DMAWM_TX_1 FIELD_PREP_CONST(ST_UART011_DMAWM_TX, 0)
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#define ST_UART011_DMAWM_TX_2 FIELD_PREP_CONST(ST_UART011_DMAWM_TX, 1)
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#define ST_UART011_DMAWM_TX_4 FIELD_PREP_CONST(ST_UART011_DMAWM_TX, 2)
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#define ST_UART011_DMAWM_TX_8 FIELD_PREP_CONST(ST_UART011_DMAWM_TX, 3)
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#define ST_UART011_DMAWM_TX_16 FIELD_PREP_CONST(ST_UART011_DMAWM_TX, 4)
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#define ST_UART011_DMAWM_TX_32 FIELD_PREP_CONST(ST_UART011_DMAWM_TX, 5)
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#define ST_UART011_DMAWM_TX_48 FIELD_PREP_CONST(ST_UART011_DMAWM_TX, 6)
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#define UART010_IIR_RTIS BIT(3)
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#define UART010_IIR_TIS BIT(2)
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#define UART010_IIR_RIS BIT(1)
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#define UART010_IIR_MIS BIT(0)
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#define UART011_IFLS_RXIFLSEL GENMASK(5, 3)
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#define UART011_IFLS_RX1_8 FIELD_PREP_CONST(UART011_IFLS_RXIFLSEL, 0)
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#define UART011_IFLS_RX2_8 FIELD_PREP_CONST(UART011_IFLS_RXIFLSEL, 1)
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#define UART011_IFLS_RX4_8 FIELD_PREP_CONST(UART011_IFLS_RXIFLSEL, 2)
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#define UART011_IFLS_RX6_8 FIELD_PREP_CONST(UART011_IFLS_RXIFLSEL, 3)
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#define UART011_IFLS_RX7_8 FIELD_PREP_CONST(UART011_IFLS_RXIFLSEL, 4)
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#define UART011_IFLS_TXIFLSEL GENMASK(2, 0)
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#define UART011_IFLS_TX1_8 FIELD_PREP_CONST(UART011_IFLS_TXIFLSEL, 0)
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#define UART011_IFLS_TX2_8 FIELD_PREP_CONST(UART011_IFLS_TXIFLSEL, 1)
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#define UART011_IFLS_TX4_8 FIELD_PREP_CONST(UART011_IFLS_TXIFLSEL, 2)
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#define UART011_IFLS_TX6_8 FIELD_PREP_CONST(UART011_IFLS_TXIFLSEL, 3)
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#define UART011_IFLS_TX7_8 FIELD_PREP_CONST(UART011_IFLS_TXIFLSEL, 4)
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/* special values for ST vendor with deeper fifo */
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#define UART011_IFLS_RX_HALF FIELD_PREP_CONST(UART011_IFLS_RXIFLSEL, 5)
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#define UART011_IFLS_TX_HALF FIELD_PREP_CONST(UART011_IFLS_TXIFLSEL, 5)
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#define UART011_OEIM BIT(10) /* overrun error interrupt mask */
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#define UART011_BEIM BIT(9) /* break error interrupt mask */
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#define UART011_PEIM BIT(8) /* parity error interrupt mask */
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#define UART011_FEIM BIT(7) /* framing error interrupt mask */
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#define UART011_RTIM BIT(6) /* receive timeout interrupt mask */
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#define UART011_TXIM BIT(5) /* transmit interrupt mask */
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#define UART011_RXIM BIT(4) /* receive interrupt mask */
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#define UART011_DSRMIM BIT(3) /* DSR interrupt mask */
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#define UART011_DCDMIM BIT(2) /* DCD interrupt mask */
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#define UART011_CTSMIM BIT(1) /* CTS interrupt mask */
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#define UART011_RIMIM BIT(0) /* RI interrupt mask */
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#define UART011_OEIS BIT(10) /* overrun error interrupt status */
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#define UART011_BEIS BIT(9) /* break error interrupt status */
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#define UART011_PEIS BIT(8) /* parity error interrupt status */
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#define UART011_FEIS BIT(7) /* framing error interrupt status */
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#define UART011_RTIS BIT(6) /* receive timeout interrupt status */
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#define UART011_TXIS BIT(5) /* transmit interrupt status */
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#define UART011_RXIS BIT(4) /* receive interrupt status */
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#define UART011_DSRMIS BIT(3) /* DSR interrupt status */
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#define UART011_DCDMIS BIT(2) /* DCD interrupt status */
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#define UART011_CTSMIS BIT(1) /* CTS interrupt status */
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#define UART011_RIMIS BIT(0) /* RI interrupt status */
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#define UART011_OEIC BIT(10) /* overrun error interrupt clear */
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#define UART011_BEIC BIT(9) /* break error interrupt clear */
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#define UART011_PEIC BIT(8) /* parity error interrupt clear */
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#define UART011_FEIC BIT(7) /* framing error interrupt clear */
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#define UART011_RTIC BIT(6) /* receive timeout interrupt clear */
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#define UART011_TXIC BIT(5) /* transmit interrupt clear */
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#define UART011_RXIC BIT(4) /* receive interrupt clear */
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#define UART011_DSRMIC BIT(3) /* DSR interrupt clear */
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#define UART011_DCDMIC BIT(2) /* DCD interrupt clear */
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#define UART011_CTSMIC BIT(1) /* CTS interrupt clear */
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#define UART011_RIMIC BIT(0) /* RI interrupt clear */
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#define UART011_DMAONERR BIT(2) /* disable dma on error */
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#define UART011_TXDMAE BIT(1) /* enable transmit dma */
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#define UART011_RXDMAE BIT(0) /* enable receive dma */
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#define UART01x_RSR_ANY (UART01x_RSR_OE | UART01x_RSR_BE | UART01x_RSR_PE | UART01x_RSR_FE)
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#define UART01x_FR_MODEM_ANY (UART01x_FR_DCD | UART01x_FR_DSR | UART01x_FR_CTS)
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#ifndef __ASSEMBLY__
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struct amba_device; /* in uncompress this is included but amba/bus.h is not */
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struct amba_pl010_data {
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void (*set_mctrl)(struct amba_device *dev, void __iomem *base, unsigned int mctrl);
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};
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struct dma_chan;
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struct amba_pl011_data {
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bool (*dma_filter)(struct dma_chan *chan, void *filter_param);
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void *dma_rx_param;
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void *dma_tx_param;
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bool dma_rx_poll_enable;
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unsigned int dma_rx_poll_rate;
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unsigned int dma_rx_poll_timeout;
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void (*init)(void);
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void (*exit)(void);
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};
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#endif
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#endif
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