forked from mirrors/linux
cc28c0e5e7
- Fix endpoint BAR testing so the test can skip disabled BARs instead of reporting them as failures (Niklas Cassel) - Verify that pci_endpoint interrupt tests set the correct IRQ type (Kunihiko Hayashi) - Fix interpretation of pci_endpoint_test_bars_read_bar() error returns (Niklas Cassel) - Fix potential string truncation in pci_endpoint_test_probe() (Niklas Cassel) - Increase endpoint test BAR size variable to accommodate BARs larger than INT_MAX (Niklas Cassel) - Release IRQs to avoid leak in pci_endpoint interrupt tests (Kunihiko Hayashi) - Log the correct IRQ type when pci_endpoint IRQ request test fails (Kunihiko Hayashi) - Remove pci_endpoint_test irq_type and no_msi globals; instead use test->irq_type (Kunihiko Hayashi) - Remove unnecessary use of managed IRQ functions in pci_endpoint_test (Kunihiko Hayashi) - Add and use IRQ_TYPE_* defines in pci_endpoint_test (Niklas Cassel) - Add struct pci_epc_features.intx_capable and note that RK3568 and RK3588 can't raise INTx interrupts (Niklas Cassel) - Expose supported IRQ types in CAPS so pci_endpoint_test can set appropriate type (Niklas Cassel) - Add PCITEST_IRQ_TYPE_AUTO to pci_endpoint_test for cases where the IRQ type doesn't matter (Niklas Cassel) * pci/endpoint-test: misc: pci_endpoint_test: Add support for PCITEST_IRQ_TYPE_AUTO PCI: endpoint: pci-epf-test: Expose supported IRQ types in CAPS register PCI: dw-rockchip: Endpoint mode cannot raise INTx interrupts PCI: endpoint: Add intx_capable to epc_features struct selftests: pci_endpoint: Use IRQ_TYPE_* defines from UAPI header misc: pci_endpoint_test: Use IRQ_TYPE_* defines from UAPI header PCI: endpoint: pcitest: Add IRQ_TYPE_* defines to UAPI header misc: pci_endpoint_test: Do not use managed IRQ functions misc: pci_endpoint_test: Remove global 'irq_type' and 'no_msi' misc: pci_endpoint_test: Fix 'irq_type' to convey the correct type misc: pci_endpoint_test: Fix displaying 'irq_type' after 'request_irq' error misc: pci_endpoint_test: Avoid issue of interrupts remaining after request_irq error misc: pci_endpoint_test: Handle BAR sizes larger than INT_MAX misc: pci_endpoint_test: Give disabled BARs a distinct error code misc: pci_endpoint_test: Fix potential truncation in pci_endpoint_test_probe() misc: pci_endpoint_test: Fix pci_endpoint_test_bars_read_bar() error handling selftests: pci_endpoint: Add GET_IRQTYPE checks to each interrupt test selftests: pci_endpoint: Skip disabled BARs
335 lines
12 KiB
C
335 lines
12 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* PCI Endpoint *Controller* (EPC) header file
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*
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* Copyright (C) 2017 Texas Instruments
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* Author: Kishon Vijay Abraham I <kishon@ti.com>
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*/
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#ifndef __LINUX_PCI_EPC_H
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#define __LINUX_PCI_EPC_H
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#include <linux/pci-epf.h>
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struct pci_epc;
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enum pci_epc_interface_type {
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UNKNOWN_INTERFACE = -1,
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PRIMARY_INTERFACE,
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SECONDARY_INTERFACE,
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};
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static inline const char *
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pci_epc_interface_string(enum pci_epc_interface_type type)
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{
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switch (type) {
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case PRIMARY_INTERFACE:
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return "primary";
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case SECONDARY_INTERFACE:
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return "secondary";
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default:
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return "UNKNOWN interface";
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}
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}
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/**
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* struct pci_epc_map - information about EPC memory for mapping a RC PCI
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* address range
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* @pci_addr: start address of the RC PCI address range to map
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* @pci_size: size of the RC PCI address range mapped from @pci_addr
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* @map_pci_addr: RC PCI address used as the first address mapped (may be lower
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* than @pci_addr)
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* @map_size: size of the controller memory needed for mapping the RC PCI address
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* range @map_pci_addr..@pci_addr+@pci_size
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* @phys_base: base physical address of the allocated EPC memory for mapping the
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* RC PCI address range
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* @phys_addr: physical address at which @pci_addr is mapped
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* @virt_base: base virtual address of the allocated EPC memory for mapping the
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* RC PCI address range
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* @virt_addr: virtual address at which @pci_addr is mapped
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*/
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struct pci_epc_map {
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u64 pci_addr;
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size_t pci_size;
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u64 map_pci_addr;
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size_t map_size;
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phys_addr_t phys_base;
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phys_addr_t phys_addr;
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void __iomem *virt_base;
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void __iomem *virt_addr;
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};
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/**
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* struct pci_epc_ops - set of function pointers for performing EPC operations
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* @write_header: ops to populate configuration space header
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* @set_bar: ops to configure the BAR
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* @clear_bar: ops to reset the BAR
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* @align_addr: operation to get the mapping address, mapping size and offset
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* into a controller memory window needed to map an RC PCI address
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* region
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* @map_addr: ops to map CPU address to PCI address
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* @unmap_addr: ops to unmap CPU address and PCI address
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* @set_msi: ops to set the requested number of MSI interrupts in the MSI
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* capability register
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* @get_msi: ops to get the number of MSI interrupts allocated by the RC from
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* the MSI capability register
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* @set_msix: ops to set the requested number of MSI-X interrupts in the
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* MSI-X capability register
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* @get_msix: ops to get the number of MSI-X interrupts allocated by the RC
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* from the MSI-X capability register
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* @raise_irq: ops to raise a legacy, MSI or MSI-X interrupt
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* @map_msi_irq: ops to map physical address to MSI address and return MSI data
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* @start: ops to start the PCI link
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* @stop: ops to stop the PCI link
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* @get_features: ops to get the features supported by the EPC
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* @owner: the module owner containing the ops
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*/
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struct pci_epc_ops {
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int (*write_header)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
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struct pci_epf_header *hdr);
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int (*set_bar)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
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struct pci_epf_bar *epf_bar);
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void (*clear_bar)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
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struct pci_epf_bar *epf_bar);
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u64 (*align_addr)(struct pci_epc *epc, u64 pci_addr, size_t *size,
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size_t *offset);
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int (*map_addr)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
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phys_addr_t addr, u64 pci_addr, size_t size);
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void (*unmap_addr)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
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phys_addr_t addr);
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int (*set_msi)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
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u8 interrupts);
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int (*get_msi)(struct pci_epc *epc, u8 func_no, u8 vfunc_no);
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int (*set_msix)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
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u16 interrupts, enum pci_barno, u32 offset);
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int (*get_msix)(struct pci_epc *epc, u8 func_no, u8 vfunc_no);
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int (*raise_irq)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
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unsigned int type, u16 interrupt_num);
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int (*map_msi_irq)(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
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phys_addr_t phys_addr, u8 interrupt_num,
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u32 entry_size, u32 *msi_data,
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u32 *msi_addr_offset);
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int (*start)(struct pci_epc *epc);
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void (*stop)(struct pci_epc *epc);
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const struct pci_epc_features* (*get_features)(struct pci_epc *epc,
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u8 func_no, u8 vfunc_no);
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struct module *owner;
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};
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/**
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* struct pci_epc_mem_window - address window of the endpoint controller
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* @phys_base: physical base address of the PCI address window
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* @size: the size of the PCI address window
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* @page_size: size of each page
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*/
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struct pci_epc_mem_window {
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phys_addr_t phys_base;
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size_t size;
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size_t page_size;
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};
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/**
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* struct pci_epc_mem - address space of the endpoint controller
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* @window: address window of the endpoint controller
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* @bitmap: bitmap to manage the PCI address space
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* @pages: number of bits representing the address region
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* @lock: mutex to protect bitmap
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*/
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struct pci_epc_mem {
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struct pci_epc_mem_window window;
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unsigned long *bitmap;
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int pages;
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/* mutex to protect against concurrent access for memory allocation*/
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struct mutex lock;
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};
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/**
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* struct pci_epc - represents the PCI EPC device
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* @dev: PCI EPC device
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* @pci_epf: list of endpoint functions present in this EPC device
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* @list_lock: Mutex for protecting pci_epf list
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* @ops: function pointers for performing endpoint operations
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* @windows: array of address space of the endpoint controller
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* @mem: first window of the endpoint controller, which corresponds to
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* default address space of the endpoint controller supporting
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* single window.
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* @num_windows: number of windows supported by device
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* @max_functions: max number of functions that can be configured in this EPC
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* @max_vfs: Array indicating the maximum number of virtual functions that can
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* be associated with each physical function
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* @group: configfs group representing the PCI EPC device
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* @lock: mutex to protect pci_epc ops
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* @function_num_map: bitmap to manage physical function number
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* @domain_nr: PCI domain number of the endpoint controller
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* @init_complete: flag to indicate whether the EPC initialization is complete
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* or not
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*/
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struct pci_epc {
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struct device dev;
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struct list_head pci_epf;
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struct mutex list_lock;
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const struct pci_epc_ops *ops;
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struct pci_epc_mem **windows;
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struct pci_epc_mem *mem;
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unsigned int num_windows;
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u8 max_functions;
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u8 *max_vfs;
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struct config_group *group;
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/* mutex to protect against concurrent access of EP controller */
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struct mutex lock;
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unsigned long function_num_map;
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int domain_nr;
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bool init_complete;
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};
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/**
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* enum pci_epc_bar_type - configurability of endpoint BAR
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* @BAR_PROGRAMMABLE: The BAR mask can be configured by the EPC.
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* @BAR_FIXED: The BAR mask is fixed by the hardware.
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* @BAR_RESIZABLE: The BAR implements the PCI-SIG Resizable BAR Capability.
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* NOTE: An EPC driver can currently only set a single supported
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* size.
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* @BAR_RESERVED: The BAR should not be touched by an EPF driver.
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*/
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enum pci_epc_bar_type {
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BAR_PROGRAMMABLE = 0,
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BAR_FIXED,
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BAR_RESIZABLE,
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BAR_RESERVED,
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};
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/**
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* struct pci_epc_bar_desc - hardware description for a BAR
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* @type: the type of the BAR
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* @fixed_size: the fixed size, only applicable if type is BAR_FIXED_MASK.
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* @only_64bit: if true, an EPF driver is not allowed to choose if this BAR
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* should be configured as 32-bit or 64-bit, the EPF driver must
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* configure this BAR as 64-bit. Additionally, the BAR succeeding
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* this BAR must be set to type BAR_RESERVED.
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*
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* only_64bit should not be set on a BAR of type BAR_RESERVED.
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* (If BARx is a 64-bit BAR that an EPF driver is not allowed to
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* touch, then both BARx and BARx+1 must be set to type
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* BAR_RESERVED.)
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*/
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struct pci_epc_bar_desc {
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enum pci_epc_bar_type type;
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u64 fixed_size;
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bool only_64bit;
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};
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/**
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* struct pci_epc_features - features supported by a EPC device per function
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* @linkup_notifier: indicate if the EPC device can notify EPF driver on link up
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* @msi_capable: indicate if the endpoint function has MSI capability
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* @msix_capable: indicate if the endpoint function has MSI-X capability
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* @intx_capable: indicate if the endpoint can raise INTx interrupts
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* @bar: array specifying the hardware description for each BAR
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* @align: alignment size required for BAR buffer allocation
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*/
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struct pci_epc_features {
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unsigned int linkup_notifier : 1;
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unsigned int msi_capable : 1;
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unsigned int msix_capable : 1;
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unsigned int intx_capable : 1;
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struct pci_epc_bar_desc bar[PCI_STD_NUM_BARS];
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size_t align;
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};
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#define to_pci_epc(device) container_of((device), struct pci_epc, dev)
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#ifdef CONFIG_PCI_ENDPOINT
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#define pci_epc_create(dev, ops) \
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__pci_epc_create((dev), (ops), THIS_MODULE)
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#define devm_pci_epc_create(dev, ops) \
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__devm_pci_epc_create((dev), (ops), THIS_MODULE)
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static inline void epc_set_drvdata(struct pci_epc *epc, void *data)
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{
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dev_set_drvdata(&epc->dev, data);
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}
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static inline void *epc_get_drvdata(struct pci_epc *epc)
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{
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return dev_get_drvdata(&epc->dev);
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}
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struct pci_epc *
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__devm_pci_epc_create(struct device *dev, const struct pci_epc_ops *ops,
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struct module *owner);
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struct pci_epc *
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__pci_epc_create(struct device *dev, const struct pci_epc_ops *ops,
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struct module *owner);
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void pci_epc_destroy(struct pci_epc *epc);
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int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf,
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enum pci_epc_interface_type type);
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void pci_epc_linkup(struct pci_epc *epc);
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void pci_epc_linkdown(struct pci_epc *epc);
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void pci_epc_init_notify(struct pci_epc *epc);
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void pci_epc_notify_pending_init(struct pci_epc *epc, struct pci_epf *epf);
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void pci_epc_deinit_notify(struct pci_epc *epc);
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void pci_epc_bus_master_enable_notify(struct pci_epc *epc);
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void pci_epc_remove_epf(struct pci_epc *epc, struct pci_epf *epf,
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enum pci_epc_interface_type type);
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int pci_epc_write_header(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
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struct pci_epf_header *hdr);
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int pci_epc_bar_size_to_rebar_cap(size_t size, u32 *cap);
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int pci_epc_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
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struct pci_epf_bar *epf_bar);
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void pci_epc_clear_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
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struct pci_epf_bar *epf_bar);
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int pci_epc_map_addr(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
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phys_addr_t phys_addr,
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u64 pci_addr, size_t size);
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void pci_epc_unmap_addr(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
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phys_addr_t phys_addr);
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int pci_epc_set_msi(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
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u8 interrupts);
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int pci_epc_get_msi(struct pci_epc *epc, u8 func_no, u8 vfunc_no);
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int pci_epc_set_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
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u16 interrupts, enum pci_barno, u32 offset);
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int pci_epc_get_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no);
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int pci_epc_map_msi_irq(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
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phys_addr_t phys_addr, u8 interrupt_num,
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u32 entry_size, u32 *msi_data, u32 *msi_addr_offset);
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int pci_epc_raise_irq(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
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unsigned int type, u16 interrupt_num);
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int pci_epc_start(struct pci_epc *epc);
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void pci_epc_stop(struct pci_epc *epc);
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const struct pci_epc_features *pci_epc_get_features(struct pci_epc *epc,
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u8 func_no, u8 vfunc_no);
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enum pci_barno
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pci_epc_get_first_free_bar(const struct pci_epc_features *epc_features);
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enum pci_barno pci_epc_get_next_free_bar(const struct pci_epc_features
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*epc_features, enum pci_barno bar);
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struct pci_epc *pci_epc_get(const char *epc_name);
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void pci_epc_put(struct pci_epc *epc);
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int pci_epc_mem_init(struct pci_epc *epc, phys_addr_t base,
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size_t size, size_t page_size);
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int pci_epc_multi_mem_init(struct pci_epc *epc,
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struct pci_epc_mem_window *window,
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unsigned int num_windows);
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void pci_epc_mem_exit(struct pci_epc *epc);
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void __iomem *pci_epc_mem_alloc_addr(struct pci_epc *epc,
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phys_addr_t *phys_addr, size_t size);
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void pci_epc_mem_free_addr(struct pci_epc *epc, phys_addr_t phys_addr,
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void __iomem *virt_addr, size_t size);
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int pci_epc_mem_map(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
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u64 pci_addr, size_t pci_size, struct pci_epc_map *map);
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void pci_epc_mem_unmap(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
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struct pci_epc_map *map);
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#else
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static inline void pci_epc_init_notify(struct pci_epc *epc)
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{
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}
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static inline void pci_epc_deinit_notify(struct pci_epc *epc)
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{
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}
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#endif /* CONFIG_PCI_ENDPOINT */
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#endif /* __LINUX_PCI_EPC_H */
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