forked from mirrors/linux
d9862cfbe2
- Support for the MIPSr6 MemoryMapID register & Global INValidate TLB (GINVT) instructions, allowing for more efficient TLB maintenance when running on a CPU such as the I6500 that supports these. - Enable huge page support for MIPS64r6. - Optimize post-DMA cache sync by removing that code entirely for kernel configurations in which we know it won't be needed. - The number of pages allocated for interrupt stacks is now calculated correctly, where before we would wastefully allocate too much memory in some configurations. - The ath79 platform migrates to devicetree. - The bcm47xx platform sees fixes for the Buffalo WHR-G54S board. - The ingenic/jz4740 platform gains support for appended devicetrees. - The cavium_octeon, lantiq, loongson32 & sgi-ip27 platforms all see cleanups as do various pieces of core architecture code. -----BEGIN PGP SIGNATURE----- iIsEABYIADMWIQRgLjeFAZEXQzy86/s+p5+stXUA3QUCXH3BQxUccGF1bC5idXJ0 b25AbWlwcy5jb20ACgkQPqefrLV1AN1+4wD+Oh4JTfZN/NEOQMlrSkXxjEHqjX3u 1Y6CiiPCs+q2UnYBANb+ic+ZH5MnvJxxmcvlYI2q3rIh4b8TDriip4KMUTUP =Sw9X -----END PGP SIGNATURE----- Merge tag 'mips_5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux Pull MIPS updates from Paul Burton: - Support for the MIPSr6 MemoryMapID register & Global INValidate TLB (GINVT) instructions, allowing for more efficient TLB maintenance when running on a CPU such as the I6500 that supports these. - Enable huge page support for MIPS64r6. - Optimize post-DMA cache sync by removing that code entirely for kernel configurations in which we know it won't be needed. - The number of pages allocated for interrupt stacks is now calculated correctly, where before we would wastefully allocate too much memory in some configurations. - The ath79 platform migrates to devicetree. - The bcm47xx platform sees fixes for the Buffalo WHR-G54S board. - The ingenic/jz4740 platform gains support for appended devicetrees. - The cavium_octeon, lantiq, loongson32 & sgi-ip27 platforms all see cleanups as do various pieces of core architecture code. * tag 'mips_5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (66 commits) MIPS: lantiq: Remove separate GPHY Firmware loader MIPS: ingenic: Add support for appended devicetree MIPS: SGI-IP27: rework HUB interrupts MIPS: SGI-IP27: do boot CPU init later MIPS: SGI-IP27: do xtalk scanning later MIPS: SGI-IP27: use pr_info/pr_emerg and pr_cont to fix output MIPS: SGI-IP27: clean up bridge access and header files MIPS: SGI-IP27: get rid of volatile and hubreg_t MIPS: irq: Allocate accurate order pages for irq stack MIPS: dma-noncoherent: Remove bogus condition in dma_sync_phys() MIPS: eBPF: Remove REG_32BIT_ZERO_EX MIPS: eBPF: Always return sign extended 32b values MIPS: CM: Fix indentation MIPS: BCM47XX: Fix/improve Buffalo WHR-G54S support MIPS: OCTEON: program rx/tx-delay always from DT MIPS: OCTEON: delete board-specific link status MIPS: OCTEON: don't lie about interface type of CN3005 board MIPS: OCTEON: warn if deprecated link status is being used MIPS: OCTEON: add fixed-link nodes to in-kernel device tree MIPS: Delete unused flush_cache_sigtramp() ...
282 lines
10 KiB
C
282 lines
10 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2006 by Ralf Baechle (ralf@linux-mips.org)
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*/
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#ifndef __ASM_BARRIER_H
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#define __ASM_BARRIER_H
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#include <asm/addrspace.h>
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/*
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* Sync types defined by the MIPS architecture (document MD00087 table 6.5)
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* These values are used with the sync instruction to perform memory barriers.
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* Types of ordering guarantees available through the SYNC instruction:
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* - Completion Barriers
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* - Ordering Barriers
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* As compared to the completion barrier, the ordering barrier is a
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* lighter-weight operation as it does not require the specified instructions
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* before the SYNC to be already completed. Instead it only requires that those
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* specified instructions which are subsequent to the SYNC in the instruction
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* stream are never re-ordered for processing ahead of the specified
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* instructions which are before the SYNC in the instruction stream.
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* This potentially reduces how many cycles the barrier instruction must stall
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* before it completes.
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* Implementations that do not use any of the non-zero values of stype to define
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* different barriers, such as ordering barriers, must make those stype values
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* act the same as stype zero.
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*/
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/*
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* Completion barriers:
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* - Every synchronizable specified memory instruction (loads or stores or both)
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* that occurs in the instruction stream before the SYNC instruction must be
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* already globally performed before any synchronizable specified memory
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* instructions that occur after the SYNC are allowed to be performed, with
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* respect to any other processor or coherent I/O module.
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*
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* - The barrier does not guarantee the order in which instruction fetches are
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* performed.
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*
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* - A stype value of zero will always be defined such that it performs the most
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* complete set of synchronization operations that are defined.This means
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* stype zero always does a completion barrier that affects both loads and
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* stores preceding the SYNC instruction and both loads and stores that are
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* subsequent to the SYNC instruction. Non-zero values of stype may be defined
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* by the architecture or specific implementations to perform synchronization
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* behaviors that are less complete than that of stype zero. If an
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* implementation does not use one of these non-zero values to define a
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* different synchronization behavior, then that non-zero value of stype must
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* act the same as stype zero completion barrier. This allows software written
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* for an implementation with a lighter-weight barrier to work on another
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* implementation which only implements the stype zero completion barrier.
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*
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* - A completion barrier is required, potentially in conjunction with SSNOP (in
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* Release 1 of the Architecture) or EHB (in Release 2 of the Architecture),
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* to guarantee that memory reference results are visible across operating
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* mode changes. For example, a completion barrier is required on some
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* implementations on entry to and exit from Debug Mode to guarantee that
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* memory effects are handled correctly.
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*/
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/*
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* stype 0 - A completion barrier that affects preceding loads and stores and
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* subsequent loads and stores.
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* Older instructions which must reach the load/store ordering point before the
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* SYNC instruction completes: Loads, Stores
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* Younger instructions which must reach the load/store ordering point only
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* after the SYNC instruction completes: Loads, Stores
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* Older instructions which must be globally performed when the SYNC instruction
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* completes: Loads, Stores
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*/
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#define STYPE_SYNC 0x0
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/*
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* Ordering barriers:
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* - Every synchronizable specified memory instruction (loads or stores or both)
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* that occurs in the instruction stream before the SYNC instruction must
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* reach a stage in the load/store datapath after which no instruction
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* re-ordering is possible before any synchronizable specified memory
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* instruction which occurs after the SYNC instruction in the instruction
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* stream reaches the same stage in the load/store datapath.
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*
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* - If any memory instruction before the SYNC instruction in program order,
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* generates a memory request to the external memory and any memory
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* instruction after the SYNC instruction in program order also generates a
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* memory request to external memory, the memory request belonging to the
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* older instruction must be globally performed before the time the memory
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* request belonging to the younger instruction is globally performed.
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*
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* - The barrier does not guarantee the order in which instruction fetches are
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* performed.
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*/
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/*
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* stype 0x10 - An ordering barrier that affects preceding loads and stores and
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* subsequent loads and stores.
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* Older instructions which must reach the load/store ordering point before the
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* SYNC instruction completes: Loads, Stores
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* Younger instructions which must reach the load/store ordering point only
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* after the SYNC instruction completes: Loads, Stores
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* Older instructions which must be globally performed when the SYNC instruction
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* completes: N/A
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*/
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#define STYPE_SYNC_MB 0x10
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/*
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* stype 0x14 - A completion barrier specific to global invalidations
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*
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* When a sync instruction of this type completes any preceding GINVI or GINVT
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* operation has been globalized & completed on all coherent CPUs. Anything
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* that the GINV* instruction should invalidate will have been invalidated on
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* all coherent CPUs when this instruction completes. It is implementation
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* specific whether the GINV* instructions themselves will ensure completion,
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* or this sync type will.
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*
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* In systems implementing global invalidates (ie. with Config5.GI == 2 or 3)
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* this sync type also requires that previous SYNCI operations have completed.
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*/
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#define STYPE_GINV 0x14
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#ifdef CONFIG_CPU_HAS_SYNC
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#define __sync() \
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__asm__ __volatile__( \
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".set push\n\t" \
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".set noreorder\n\t" \
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".set mips2\n\t" \
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"sync\n\t" \
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".set pop" \
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: /* no output */ \
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: /* no input */ \
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: "memory")
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#else
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#define __sync() do { } while(0)
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#endif
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#define __fast_iob() \
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__asm__ __volatile__( \
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".set push\n\t" \
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".set noreorder\n\t" \
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"lw $0,%0\n\t" \
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"nop\n\t" \
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".set pop" \
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: /* no output */ \
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: "m" (*(int *)CKSEG1) \
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: "memory")
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#ifdef CONFIG_CPU_CAVIUM_OCTEON
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# define OCTEON_SYNCW_STR ".set push\n.set arch=octeon\nsyncw\nsyncw\n.set pop\n"
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# define __syncw() __asm__ __volatile__(OCTEON_SYNCW_STR : : : "memory")
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# define fast_wmb() __syncw()
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# define fast_rmb() barrier()
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# define fast_mb() __sync()
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# define fast_iob() do { } while (0)
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#else /* ! CONFIG_CPU_CAVIUM_OCTEON */
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# define fast_wmb() __sync()
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# define fast_rmb() __sync()
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# define fast_mb() __sync()
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# ifdef CONFIG_SGI_IP28
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# define fast_iob() \
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__asm__ __volatile__( \
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".set push\n\t" \
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".set noreorder\n\t" \
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"lw $0,%0\n\t" \
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"sync\n\t" \
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"lw $0,%0\n\t" \
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".set pop" \
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: /* no output */ \
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: "m" (*(int *)CKSEG1ADDR(0x1fa00004)) \
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: "memory")
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# else
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# define fast_iob() \
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do { \
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__sync(); \
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__fast_iob(); \
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} while (0)
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# endif
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#endif /* CONFIG_CPU_CAVIUM_OCTEON */
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#ifdef CONFIG_CPU_HAS_WB
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#include <asm/wbflush.h>
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#define mb() wbflush()
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#define iob() wbflush()
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#else /* !CONFIG_CPU_HAS_WB */
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#define mb() fast_mb()
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#define iob() fast_iob()
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#endif /* !CONFIG_CPU_HAS_WB */
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#define wmb() fast_wmb()
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#define rmb() fast_rmb()
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#if defined(CONFIG_WEAK_ORDERING)
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# ifdef CONFIG_CPU_CAVIUM_OCTEON
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# define __smp_mb() __sync()
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# define __smp_rmb() barrier()
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# define __smp_wmb() __syncw()
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# else
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# define __smp_mb() __asm__ __volatile__("sync" : : :"memory")
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# define __smp_rmb() __asm__ __volatile__("sync" : : :"memory")
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# define __smp_wmb() __asm__ __volatile__("sync" : : :"memory")
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# endif
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#else
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#define __smp_mb() barrier()
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#define __smp_rmb() barrier()
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#define __smp_wmb() barrier()
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#endif
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#if defined(CONFIG_WEAK_REORDERING_BEYOND_LLSC) && defined(CONFIG_SMP)
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#define __WEAK_LLSC_MB " sync \n"
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#else
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#define __WEAK_LLSC_MB " \n"
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#endif
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#define smp_llsc_mb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory")
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#ifdef CONFIG_CPU_CAVIUM_OCTEON
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#define smp_mb__before_llsc() smp_wmb()
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#define __smp_mb__before_llsc() __smp_wmb()
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/* Cause previous writes to become visible on all CPUs as soon as possible */
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#define nudge_writes() __asm__ __volatile__(".set push\n\t" \
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".set arch=octeon\n\t" \
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"syncw\n\t" \
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".set pop" : : : "memory")
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#else
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#define smp_mb__before_llsc() smp_llsc_mb()
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#define __smp_mb__before_llsc() smp_llsc_mb()
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#define nudge_writes() mb()
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#endif
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#define __smp_mb__before_atomic() __smp_mb__before_llsc()
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#define __smp_mb__after_atomic() smp_llsc_mb()
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/*
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* Some Loongson 3 CPUs have a bug wherein execution of a memory access (load,
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* store or pref) in between an ll & sc can cause the sc instruction to
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* erroneously succeed, breaking atomicity. Whilst it's unusual to write code
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* containing such sequences, this bug bites harder than we might otherwise
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* expect due to reordering & speculation:
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*
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* 1) A memory access appearing prior to the ll in program order may actually
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* be executed after the ll - this is the reordering case.
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*
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* In order to avoid this we need to place a memory barrier (ie. a sync
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* instruction) prior to every ll instruction, in between it & any earlier
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* memory access instructions. Many of these cases are already covered by
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* smp_mb__before_llsc() but for the remaining cases, typically ones in
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* which multiple CPUs may operate on a memory location but ordering is not
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* usually guaranteed, we use loongson_llsc_mb() below.
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*
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* This reordering case is fixed by 3A R2 CPUs, ie. 3A2000 models and later.
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*
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* 2) If a conditional branch exists between an ll & sc with a target outside
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* of the ll-sc loop, for example an exit upon value mismatch in cmpxchg()
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* or similar, then misprediction of the branch may allow speculative
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* execution of memory accesses from outside of the ll-sc loop.
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*
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* In order to avoid this we need a memory barrier (ie. a sync instruction)
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* at each affected branch target, for which we also use loongson_llsc_mb()
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* defined below.
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*
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* This case affects all current Loongson 3 CPUs.
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*/
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#ifdef CONFIG_CPU_LOONGSON3_WORKAROUNDS /* Loongson-3's LLSC workaround */
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#define loongson_llsc_mb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory")
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#else
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#define loongson_llsc_mb() do { } while (0)
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#endif
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static inline void sync_ginv(void)
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{
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asm volatile("sync\t%0" :: "i"(STYPE_GINV));
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}
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#include <asm-generic/barrier.h>
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#endif /* __ASM_BARRIER_H */
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