forked from mirrors/linux
72ae6e4b31
Peripheral handshaking identification numbers can be bigger than 15, so new fields have been created in the CFG register. Add macros to take this modification into account and use them in at_dma_xlate() function. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
65 lines
2.5 KiB
C
65 lines
2.5 KiB
C
/*
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* Header file for the Atmel AHB DMA Controller driver
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*
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* Copyright (C) 2008 Atmel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef AT_HDMAC_H
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#define AT_HDMAC_H
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#include <linux/dmaengine.h>
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/**
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* struct at_dma_platform_data - Controller configuration parameters
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* @nr_channels: Number of channels supported by hardware (max 8)
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* @cap_mask: dma_capability flags supported by the platform
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*/
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struct at_dma_platform_data {
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unsigned int nr_channels;
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dma_cap_mask_t cap_mask;
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};
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/**
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* struct at_dma_slave - Controller-specific information about a slave
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* @dma_dev: required DMA master device
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* @cfg: Platform-specific initializer for the CFG register
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*/
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struct at_dma_slave {
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struct device *dma_dev;
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u32 cfg;
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};
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/* Platform-configurable bits in CFG */
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#define ATC_PER_MSB(h) ((0x30U & (h)) >> 4) /* Extract most significant bits of a handshaking identifier */
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#define ATC_SRC_PER(h) (0xFU & (h)) /* Channel src rq associated with periph handshaking ifc h */
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#define ATC_DST_PER(h) ((0xFU & (h)) << 4) /* Channel dst rq associated with periph handshaking ifc h */
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#define ATC_SRC_REP (0x1 << 8) /* Source Replay Mod */
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#define ATC_SRC_H2SEL (0x1 << 9) /* Source Handshaking Mod */
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#define ATC_SRC_H2SEL_SW (0x0 << 9)
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#define ATC_SRC_H2SEL_HW (0x1 << 9)
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#define ATC_SRC_PER_MSB(h) (ATC_PER_MSB(h) << 10) /* Channel src rq (most significant bits) */
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#define ATC_DST_REP (0x1 << 12) /* Destination Replay Mod */
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#define ATC_DST_H2SEL (0x1 << 13) /* Destination Handshaking Mod */
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#define ATC_DST_H2SEL_SW (0x0 << 13)
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#define ATC_DST_H2SEL_HW (0x1 << 13)
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#define ATC_DST_PER_MSB(h) (ATC_PER_MSB(h) << 14) /* Channel dst rq (most significant bits) */
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#define ATC_SOD (0x1 << 16) /* Stop On Done */
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#define ATC_LOCK_IF (0x1 << 20) /* Interface Lock */
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#define ATC_LOCK_B (0x1 << 21) /* AHB Bus Lock */
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#define ATC_LOCK_IF_L (0x1 << 22) /* Master Interface Arbiter Lock */
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#define ATC_LOCK_IF_L_CHUNK (0x0 << 22)
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#define ATC_LOCK_IF_L_BUFFER (0x1 << 22)
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#define ATC_AHB_PROT_MASK (0x7 << 24) /* AHB Protection */
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#define ATC_FIFOCFG_MASK (0x3 << 28) /* FIFO Request Configuration */
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#define ATC_FIFOCFG_LARGESTBURST (0x0 << 28)
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#define ATC_FIFOCFG_HALFFIFO (0x1 << 28)
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#define ATC_FIFOCFG_ENOUGHSPACE (0x2 << 28)
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#endif /* AT_HDMAC_H */
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