forked from mirrors/linux
		
	 ad4e600cbf
			
		
	
	
		ad4e600cbf
		
	
	
	
	
		
			
			Since upstream LiteX recommends that Linux support be limited to designs configured with 32-bit CSR subregisters (see commit a2b71fde in upstream LiteX, https://github.com/enjoy-digital/litex), remove the option to select 8-bit subregisters, significantly reducing the complexity of LiteX CSR (MMIO register) accessor methods. NOTE: for details on the underlying mechanics of LiteX CSR registers, see https://github.com/enjoy-digital/litex/wiki/CSR-Bus or the original LiteX accessors (litex/soc/software/include/hw/common.h in the upstream repository). Signed-off-by: Gabriel Somlo <gsomlo@gmail.com> Cc: Stafford Horne <shorne@gmail.com> Cc: Florent Kermarrec <florent@enjoy-digital.fr> Cc: Mateusz Holenko <mholenko@antmicro.com> Cc: Joel Stanley <joel@jms.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Stafford Horne <shorne@gmail.com>
		
			
				
	
	
		
			83 lines
		
	
	
	
		
			2.1 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			83 lines
		
	
	
	
		
			2.1 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /* SPDX-License-Identifier: GPL-2.0 */
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| /*
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|  * Common LiteX header providing
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|  * helper functions for accessing CSRs.
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|  *
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|  * Copyright (C) 2019-2020 Antmicro <www.antmicro.com>
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|  */
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| 
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| #ifndef _LINUX_LITEX_H
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| #define _LINUX_LITEX_H
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| 
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| #include <linux/io.h>
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| 
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| static inline void _write_litex_subregister(u32 val, void __iomem *addr)
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| {
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| 	writel((u32 __force)cpu_to_le32(val), addr);
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| }
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| 
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| static inline u32 _read_litex_subregister(void __iomem *addr)
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| {
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| 	return le32_to_cpu((__le32 __force)readl(addr));
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| }
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| 
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| /*
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|  * LiteX SoC Generator, depending on the configuration, can split a single
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|  * logical CSR (Control&Status Register) into a series of consecutive physical
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|  * registers.
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|  *
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|  * For example, in the configuration with 8-bit CSR Bus, a 32-bit aligned,
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|  * 32-bit wide logical CSR will be laid out as four 32-bit physical
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|  * subregisters, each one containing one byte of meaningful data.
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|  *
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|  * For Linux support, upstream LiteX enforces a 32-bit wide CSR bus, which
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|  * means that only larger-than-32-bit CSRs will be split across multiple
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|  * subregisters (e.g., a 64-bit CSR will be spread across two consecutive
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|  * 32-bit subregisters).
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|  *
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|  * For details see: https://github.com/enjoy-digital/litex/wiki/CSR-Bus
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|  */
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| 
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| static inline void litex_write8(void __iomem *reg, u8 val)
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| {
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| 	_write_litex_subregister(val, reg);
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| }
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| 
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| static inline void litex_write16(void __iomem *reg, u16 val)
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| {
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| 	_write_litex_subregister(val, reg);
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| }
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| 
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| static inline void litex_write32(void __iomem *reg, u32 val)
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| {
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| 	_write_litex_subregister(val, reg);
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| }
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| 
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| static inline void litex_write64(void __iomem *reg, u64 val)
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| {
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| 	_write_litex_subregister(val >> 32, reg);
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| 	_write_litex_subregister(val, reg + 4);
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| }
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| 
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| static inline u8 litex_read8(void __iomem *reg)
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| {
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| 	return _read_litex_subregister(reg);
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| }
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| 
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| static inline u16 litex_read16(void __iomem *reg)
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| {
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| 	return _read_litex_subregister(reg);
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| }
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| 
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| static inline u32 litex_read32(void __iomem *reg)
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| {
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| 	return _read_litex_subregister(reg);
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| }
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| 
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| static inline u64 litex_read64(void __iomem *reg)
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| {
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| 	return ((u64)_read_litex_subregister(reg) << 32) |
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| 		_read_litex_subregister(reg + 4);
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| }
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| 
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| #endif /* _LINUX_LITEX_H */
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