forked from mirrors/linux
fe4e9ff987
MES requires mc wptr address for usermode queues. Export bo gart address for mc wptr address. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
122 lines
3.4 KiB
C
122 lines
3.4 KiB
C
/*
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* Copyright 2019 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __AMDGPU_MES_CTX_H__
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#define __AMDGPU_MES_CTX_H__
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#include "v10_structs.h"
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enum {
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AMDGPU_MES_CTX_RPTR_OFFS = 0,
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AMDGPU_MES_CTX_WPTR_OFFS,
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AMDGPU_MES_CTX_FENCE_OFFS,
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AMDGPU_MES_CTX_COND_EXE_OFFS,
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AMDGPU_MES_CTX_TRAIL_FENCE_OFFS,
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AMDGPU_MES_CTX_MAX_OFFS,
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};
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enum {
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AMDGPU_MES_CTX_RING_OFFS = AMDGPU_MES_CTX_MAX_OFFS,
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AMDGPU_MES_CTX_IB_OFFS,
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AMDGPU_MES_CTX_PADDING_OFFS,
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};
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#define AMDGPU_MES_CTX_MAX_GFX_RINGS 1
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#define AMDGPU_MES_CTX_MAX_COMPUTE_RINGS 4
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#define AMDGPU_MES_CTX_MAX_SDMA_RINGS 2
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#define AMDGPU_MES_CTX_MAX_RINGS \
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(AMDGPU_MES_CTX_MAX_GFX_RINGS + \
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AMDGPU_MES_CTX_MAX_COMPUTE_RINGS + \
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AMDGPU_MES_CTX_MAX_SDMA_RINGS)
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#define AMDGPU_CSA_SDMA_SIZE 64
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#define GFX10_MEC_HPD_SIZE 2048
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struct amdgpu_wb_slot {
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uint32_t data[8];
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};
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struct amdgpu_mes_ctx_meta_data {
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struct {
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uint8_t ring[PAGE_SIZE * 4];
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/* gfx csa */
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struct v10_gfx_meta_data gfx_meta_data;
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uint8_t gds_backup[64 * 1024];
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struct amdgpu_wb_slot slots[AMDGPU_MES_CTX_MAX_OFFS];
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/* only for ib test */
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uint32_t ib[256] __aligned(256);
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uint32_t padding[64];
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} __aligned(PAGE_SIZE) gfx[AMDGPU_MES_CTX_MAX_GFX_RINGS];
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struct {
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uint8_t ring[PAGE_SIZE * 4];
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uint8_t mec_hpd[GFX10_MEC_HPD_SIZE];
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struct amdgpu_wb_slot slots[AMDGPU_MES_CTX_MAX_OFFS];
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/* only for ib test */
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uint32_t ib[256] __aligned(256);
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uint32_t padding[64];
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} __aligned(PAGE_SIZE) compute[AMDGPU_MES_CTX_MAX_COMPUTE_RINGS];
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struct {
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uint8_t ring[PAGE_SIZE * 4];
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/* sdma csa for mcbp */
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uint8_t sdma_meta_data[AMDGPU_CSA_SDMA_SIZE];
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struct amdgpu_wb_slot slots[AMDGPU_MES_CTX_MAX_OFFS];
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/* only for ib test */
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uint32_t ib[256] __aligned(256);
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uint32_t padding[64];
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} __aligned(PAGE_SIZE) sdma[AMDGPU_MES_CTX_MAX_SDMA_RINGS];
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};
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struct amdgpu_mes_ctx_data {
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struct amdgpu_bo *meta_data_obj;
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uint64_t meta_data_gpu_addr;
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uint64_t meta_data_mc_addr;
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struct amdgpu_bo_va *meta_data_va;
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void *meta_data_ptr;
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uint32_t gang_ids[AMDGPU_HW_IP_DMA+1];
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};
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#define AMDGPU_FENCE_MES_QUEUE_FLAG 0x1000000u
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#define AMDGPU_FENCE_MES_QUEUE_ID_MASK (AMDGPU_FENCE_MES_QUEUE_FLAG - 1)
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#define AMDGPU_FENCE_MES_QUEUE_FLAG 0x1000000u
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#define AMDGPU_FENCE_MES_QUEUE_ID_MASK (AMDGPU_FENCE_MES_QUEUE_FLAG - 1)
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#endif
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