forked from mirrors/linux
d6a322774c
This round we have few new features, new driver and updates to few drivers.
The new features to dmaengine core are:
- Synchronized transfer termination API to terminate the dmaengine
transfers in synchronized and async fashion as required by users.
We have its user now in ALSA dmaengine lib, img, at_xdma, axi_dmac
drivers.
- Universal API for channel request and start consolidation of request
flows. It's user is ompa-dma driver.
- Introduce reuse of descriptors and use in pxa_dma driver
Add/Remove:
- STM32 DMA driver
- Removal of unused R-Car HPB-DMAC driver
Updates:
- ti-dma-crossbar updates for supporting eDMA
- tegra-apb pm updates
- idma64
- mv_xor updates
- ste_dma updates
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Merge tag 'dmaengine-4.5-rc1' of git://git.infradead.org/users/vkoul/slave-dma
Pull dmaengine updates from Vinod Koul:
"This round we have few new features, new driver and updates to few
drivers.
The new features to dmaengine core are:
- Synchronized transfer termination API to terminate the dmaengine
transfers in synchronized and async fashion as required by users.
We have its user now in ALSA dmaengine lib, img, at_xdma, axi_dmac
drivers.
- Universal API for channel request and start consolidation of
request flows. It's user is ompa-dma driver.
- Introduce reuse of descriptors and use in pxa_dma driver
Add/Remove:
- New STM32 DMA driver
- Removal of unused R-Car HPB-DMAC driver
Updates:
- ti-dma-crossbar updates for supporting eDMA
- tegra-apb pm updates
- idma64
- mv_xor updates
- ste_dma updates"
* tag 'dmaengine-4.5-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (54 commits)
dmaengine: mv_xor: add suspend/resume support
dmaengine: mv_xor: de-duplicate mv_chan_set_mode*()
dmaengine: mv_xor: remove mv_xor_chan->current_type field
dmaengine: omap-dma: Add support for DMA filter mapping to slave devices
dmaengine: edma: Add support for DMA filter mapping to slave devices
dmaengine: core: Introduce new, universal API to request a channel
dmaengine: core: Move and merge the code paths using private_candidate
dmaengine: core: Skip mask matching when it is not provided to private_candidate
dmaengine: mdc: Correct terminate_all handling
dmaengine: edma: Add probe callback to edma_tptc_driver
dmaengine: dw: fix potential memory leak in dw_dma_parse_dt()
dmaengine: stm32-dma: Fix unchecked deference of chan->desc
dmaengine: sh: Remove unused R-Car HPB-DMAC driver
dmaengine: usb-dmac: Document SoC specific compatibility strings
ste_dma40: Delete an unnecessary variable initialisation in d40_probe()
ste_dma40: Delete another unnecessary check in d40_probe()
ste_dma40: Delete an unnecessary check before the function call "kmem_cache_destroy"
dmaengine: tegra-apb: Free interrupts before killing tasklets
dmaengine: tegra-apb: Update driver to use GFP_NOWAIT
dmaengine: tegra-apb: Only save channel state for those in use
...
88 lines
2.7 KiB
C
88 lines
2.7 KiB
C
/*
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* TI EDMA definitions
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*
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* Copyright (C) 2006-2013 Texas Instruments.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/*
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* This EDMA3 programming framework exposes two basic kinds of resource:
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*
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* Channel Triggers transfers, usually from a hardware event but
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* also manually or by "chaining" from DMA completions.
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* Each channel is coupled to a Parameter RAM (PaRAM) slot.
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*
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* Slot Each PaRAM slot holds a DMA transfer descriptor (PaRAM
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* "set"), source and destination addresses, a link to a
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* next PaRAM slot (if any), options for the transfer, and
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* instructions for updating those addresses. There are
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* more than twice as many slots as event channels.
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*
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* Each PaRAM set describes a sequence of transfers, either for one large
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* buffer or for several discontiguous smaller buffers. An EDMA transfer
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* is driven only from a channel, which performs the transfers specified
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* in its PaRAM slot until there are no more transfers. When that last
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* transfer completes, the "link" field may be used to reload the channel's
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* PaRAM slot with a new transfer descriptor.
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*
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* The EDMA Channel Controller (CC) maps requests from channels into physical
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* Transfer Controller (TC) requests when the channel triggers (by hardware
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* or software events, or by chaining). The two physical DMA channels provided
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* by the TCs are thus shared by many logical channels.
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*
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* DaVinci hardware also has a "QDMA" mechanism which is not currently
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* supported through this interface. (DSP firmware uses it though.)
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*/
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#ifndef EDMA_H_
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#define EDMA_H_
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enum dma_event_q {
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EVENTQ_0 = 0,
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EVENTQ_1 = 1,
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EVENTQ_2 = 2,
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EVENTQ_3 = 3,
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EVENTQ_DEFAULT = -1
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};
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#define EDMA_CTLR_CHAN(ctlr, chan) (((ctlr) << 16) | (chan))
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#define EDMA_CTLR(i) ((i) >> 16)
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#define EDMA_CHAN_SLOT(i) ((i) & 0xffff)
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#define EDMA_FILTER_PARAM(ctlr, chan) ((int[]) { EDMA_CTLR_CHAN(ctlr, chan) })
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struct edma_rsv_info {
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const s16 (*rsv_chans)[2];
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const s16 (*rsv_slots)[2];
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};
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struct dma_slave_map;
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/* platform_data for EDMA driver */
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struct edma_soc_info {
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/*
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* Default queue is expected to be a low-priority queue.
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* This way, long transfers on the default queue started
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* by the codec engine will not cause audio defects.
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*/
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enum dma_event_q default_queue;
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/* Resource reservation for other cores */
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struct edma_rsv_info *rsv;
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/* List of channels allocated for memcpy, terminated with -1 */
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s32 *memcpy_channels;
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s8 (*queue_priority_mapping)[2];
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const s16 (*xbar_chans)[2];
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const struct dma_slave_map *slave_map;
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int slavecnt;
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};
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#endif
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