forked from mirrors/linux
ae65a26dd3
META-DATA is used in GFX cmd submit, we have two format suit for META-DATA-init, one is legacy and another is for chained-ib preempt, which is used in vulkan UMD. v2: drop use CP version number to judge if chain-ib supports or not, we wait for it mature Signed-off-by: Monk Liu <Monk.Liu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
143 lines
4.6 KiB
C
143 lines
4.6 KiB
C
/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __VI_H__
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#define __VI_H__
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void vi_srbm_select(struct amdgpu_device *adev,
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u32 me, u32 pipe, u32 queue, u32 vmid);
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int vi_set_ip_blocks(struct amdgpu_device *adev);
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struct amdgpu_ce_ib_state
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{
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uint32_t ce_ib_completion_status;
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uint32_t ce_constegnine_count;
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uint32_t ce_ibOffset_ib1;
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uint32_t ce_ibOffset_ib2;
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}; /* Total of 4 DWORD */
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struct amdgpu_de_ib_state
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{
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uint32_t ib_completion_status;
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uint32_t de_constEngine_count;
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uint32_t ib_offset_ib1;
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uint32_t ib_offset_ib2;
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uint32_t preamble_begin_ib1;
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uint32_t preamble_begin_ib2;
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uint32_t preamble_end_ib1;
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uint32_t preamble_end_ib2;
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uint32_t draw_indirect_baseLo;
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uint32_t draw_indirect_baseHi;
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uint32_t disp_indirect_baseLo;
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uint32_t disp_indirect_baseHi;
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uint32_t gds_backup_addrlo;
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uint32_t gds_backup_addrhi;
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uint32_t index_base_addrlo;
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uint32_t index_base_addrhi;
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uint32_t sample_cntl;
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}; /* Total of 17 DWORD */
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struct amdgpu_ce_ib_state_chained_ib
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{
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/* section of non chained ib part */
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uint32_t ce_ib_completion_status;
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uint32_t ce_constegnine_count;
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uint32_t ce_ibOffset_ib1;
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uint32_t ce_ibOffset_ib2;
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/* section of chained ib */
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uint32_t ce_chainib_addrlo_ib1;
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uint32_t ce_chainib_addrlo_ib2;
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uint32_t ce_chainib_addrhi_ib1;
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uint32_t ce_chainib_addrhi_ib2;
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uint32_t ce_chainib_size_ib1;
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uint32_t ce_chainib_size_ib2;
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}; /* total 10 DWORD */
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struct amdgpu_de_ib_state_chained_ib
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{
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/* section of non chained ib part */
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uint32_t ib_completion_status;
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uint32_t de_constEngine_count;
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uint32_t ib_offset_ib1;
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uint32_t ib_offset_ib2;
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/* section of chained ib */
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uint32_t chain_ib_addrlo_ib1;
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uint32_t chain_ib_addrlo_ib2;
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uint32_t chain_ib_addrhi_ib1;
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uint32_t chain_ib_addrhi_ib2;
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uint32_t chain_ib_size_ib1;
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uint32_t chain_ib_size_ib2;
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/* section of non chained ib part */
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uint32_t preamble_begin_ib1;
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uint32_t preamble_begin_ib2;
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uint32_t preamble_end_ib1;
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uint32_t preamble_end_ib2;
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/* section of chained ib */
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uint32_t chain_ib_pream_addrlo_ib1;
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uint32_t chain_ib_pream_addrlo_ib2;
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uint32_t chain_ib_pream_addrhi_ib1;
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uint32_t chain_ib_pream_addrhi_ib2;
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/* section of non chained ib part */
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uint32_t draw_indirect_baseLo;
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uint32_t draw_indirect_baseHi;
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uint32_t disp_indirect_baseLo;
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uint32_t disp_indirect_baseHi;
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uint32_t gds_backup_addrlo;
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uint32_t gds_backup_addrhi;
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uint32_t index_base_addrlo;
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uint32_t index_base_addrhi;
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uint32_t sample_cntl;
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}; /* Total of 27 DWORD */
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struct amdgpu_gfx_meta_data
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{
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/* 4 DWORD, address must be 4KB aligned */
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struct amdgpu_ce_ib_state ce_payload;
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uint32_t reserved1[60];
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/* 17 DWORD, address must be 64B aligned */
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struct amdgpu_de_ib_state de_payload;
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/* PFP IB base address which get pre-empted */
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uint32_t DeIbBaseAddrLo;
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uint32_t DeIbBaseAddrHi;
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uint32_t reserved2[941];
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}; /* Total of 4K Bytes */
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struct amdgpu_gfx_meta_data_chained_ib
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{
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/* 10 DWORD, address must be 4KB aligned */
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struct amdgpu_ce_ib_state_chained_ib ce_payload;
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uint32_t reserved1[54];
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/* 27 DWORD, address must be 64B aligned */
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struct amdgpu_de_ib_state_chained_ib de_payload;
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/* PFP IB base address which get pre-empted */
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uint32_t DeIbBaseAddrLo;
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uint32_t DeIbBaseAddrHi;
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uint32_t reserved2[931];
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}; /* Total of 4K Bytes */
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#endif
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