forked from mirrors/linux
d5e2d00898
Highlights:
- Restructure Linux PTE on Book3S/64 to Radix format from Paul Mackerras
- Book3s 64 MMU cleanup in preparation for Radix MMU from Aneesh Kumar K.V
- Add POWER9 cputable entry from Michael Neuling
- FPU/Altivec/VSX save/restore optimisations from Cyril Bur
- Add support for new ftrace ABI on ppc64le from Torsten Duwe
Various cleanups & minor fixes from:
- Adam Buchbinder, Andrew Donnellan, Balbir Singh, Christophe Leroy, Cyril
Bur, Luis Henriques, Madhavan Srinivasan, Pan Xinhui, Russell Currey,
Sukadev Bhattiprolu, Suraj Jitindar Singh.
General:
- atomics: Allow architectures to define their own __atomic_op_* helpers from
Boqun Feng
- Implement atomic{, 64}_*_return_* variants and acquire/release/relaxed
variants for (cmp)xchg from Boqun Feng
- Add powernv_defconfig from Jeremy Kerr
- Fix BUG_ON() reporting in real mode from Balbir Singh
- Add xmon command to dump OPAL msglog from Andrew Donnellan
- Add xmon command to dump process/task similar to ps(1) from Douglas Miller
- Clean up memory hotplug failure paths from David Gibson
pci/eeh:
- Redesign SR-IOV on PowerNV to give absolute isolation between VFs from Wei
Yang.
- EEH Support for SRIOV VFs from Wei Yang and Gavin Shan.
- PCI/IOV: Rename and export virtfn_{add, remove} from Wei Yang
- PCI: Add pcibios_bus_add_device() weak function from Wei Yang
- MAINTAINERS: Update EEH details and maintainership from Russell Currey
cxl:
- Support added to the CXL driver for running on both bare-metal and
hypervisor systems, from Christophe Lombard and Frederic Barrat.
- Ignore probes for virtual afu pci devices from Vaibhav Jain
perf:
- Export Power8 generic and cache events to sysfs from Sukadev Bhattiprolu
- hv-24x7: Fix usage with chip events, display change in counter values,
display domain indices in sysfs, eliminate domain suffix in event names,
from Sukadev Bhattiprolu
Freescale:
- Updates from Scott: "Highlights include 8xx optimizations, 32-bit checksum
optimizations, 86xx consolidation, e5500/e6500 cpu hotplug, more fman and
other dt bits, and minor fixes/cleanup."
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Merge tag 'powerpc-4.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux
Pull powerpc updates from Michael Ellerman:
"This was delayed a day or two by some build-breakage on old toolchains
which we've now fixed.
There's two PCI commits both acked by Bjorn.
There's one commit to mm/hugepage.c which is (co)authored by Kirill.
Highlights:
- Restructure Linux PTE on Book3S/64 to Radix format from Paul
Mackerras
- Book3s 64 MMU cleanup in preparation for Radix MMU from Aneesh
Kumar K.V
- Add POWER9 cputable entry from Michael Neuling
- FPU/Altivec/VSX save/restore optimisations from Cyril Bur
- Add support for new ftrace ABI on ppc64le from Torsten Duwe
Various cleanups & minor fixes from:
- Adam Buchbinder, Andrew Donnellan, Balbir Singh, Christophe Leroy,
Cyril Bur, Luis Henriques, Madhavan Srinivasan, Pan Xinhui, Russell
Currey, Sukadev Bhattiprolu, Suraj Jitindar Singh.
General:
- atomics: Allow architectures to define their own __atomic_op_*
helpers from Boqun Feng
- Implement atomic{, 64}_*_return_* variants and acquire/release/
relaxed variants for (cmp)xchg from Boqun Feng
- Add powernv_defconfig from Jeremy Kerr
- Fix BUG_ON() reporting in real mode from Balbir Singh
- Add xmon command to dump OPAL msglog from Andrew Donnellan
- Add xmon command to dump process/task similar to ps(1) from Douglas
Miller
- Clean up memory hotplug failure paths from David Gibson
pci/eeh:
- Redesign SR-IOV on PowerNV to give absolute isolation between VFs
from Wei Yang.
- EEH Support for SRIOV VFs from Wei Yang and Gavin Shan.
- PCI/IOV: Rename and export virtfn_{add, remove} from Wei Yang
- PCI: Add pcibios_bus_add_device() weak function from Wei Yang
- MAINTAINERS: Update EEH details and maintainership from Russell
Currey
cxl:
- Support added to the CXL driver for running on both bare-metal and
hypervisor systems, from Christophe Lombard and Frederic Barrat.
- Ignore probes for virtual afu pci devices from Vaibhav Jain
perf:
- Export Power8 generic and cache events to sysfs from Sukadev
Bhattiprolu
- hv-24x7: Fix usage with chip events, display change in counter
values, display domain indices in sysfs, eliminate domain suffix in
event names, from Sukadev Bhattiprolu
Freescale:
- Updates from Scott: "Highlights include 8xx optimizations, 32-bit
checksum optimizations, 86xx consolidation, e5500/e6500 cpu
hotplug, more fman and other dt bits, and minor fixes/cleanup"
* tag 'powerpc-4.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux: (179 commits)
powerpc: Fix unrecoverable SLB miss during restore_math()
powerpc/8xx: Fix do_mtspr_cpu6() build on older compilers
powerpc/rcpm: Fix build break when SMP=n
powerpc/book3e-64: Use hardcoded mttmr opcode
powerpc/fsl/dts: Add "jedec,spi-nor" flash compatible
powerpc/T104xRDB: add tdm riser card node to device tree
powerpc32: PAGE_EXEC required for inittext
powerpc/mpc85xx: Add pcsphy nodes to FManV3 device tree
powerpc/mpc85xx: Add MDIO bus muxing support to the board device tree(s)
powerpc/86xx: Introduce and use common dtsi
powerpc/86xx: Update device tree
powerpc/86xx: Move dts files to fsl directory
powerpc/86xx: Switch to kconfig fragments approach
powerpc/86xx: Update defconfigs
powerpc/86xx: Consolidate common platform code
powerpc32: Remove one insn in mulhdu
powerpc32: small optimisation in flush_icache_range()
powerpc: Simplify test in __dma_sync()
powerpc32: move xxxxx_dcache_range() functions inline
powerpc32: Remove clear_pages() and define clear_page() inline
...
595 lines
16 KiB
C
595 lines
16 KiB
C
/* Atomic operations usable in machine independent code */
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#ifndef _LINUX_ATOMIC_H
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#define _LINUX_ATOMIC_H
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#include <asm/atomic.h>
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#include <asm/barrier.h>
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/*
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* Relaxed variants of xchg, cmpxchg and some atomic operations.
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*
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* We support four variants:
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*
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* - Fully ordered: The default implementation, no suffix required.
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* - Acquire: Provides ACQUIRE semantics, _acquire suffix.
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* - Release: Provides RELEASE semantics, _release suffix.
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* - Relaxed: No ordering guarantees, _relaxed suffix.
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*
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* For compound atomics performing both a load and a store, ACQUIRE
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* semantics apply only to the load and RELEASE semantics only to the
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* store portion of the operation. Note that a failed cmpxchg_acquire
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* does -not- imply any memory ordering constraints.
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*
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* See Documentation/memory-barriers.txt for ACQUIRE/RELEASE definitions.
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*/
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#ifndef atomic_read_acquire
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#define atomic_read_acquire(v) smp_load_acquire(&(v)->counter)
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#endif
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#ifndef atomic_set_release
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#define atomic_set_release(v, i) smp_store_release(&(v)->counter, (i))
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#endif
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/*
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* The idea here is to build acquire/release variants by adding explicit
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* barriers on top of the relaxed variant. In the case where the relaxed
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* variant is already fully ordered, no additional barriers are needed.
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*
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* Besides, if an arch has a special barrier for acquire/release, it could
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* implement its own __atomic_op_* and use the same framework for building
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* variants
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*/
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#ifndef __atomic_op_acquire
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#define __atomic_op_acquire(op, args...) \
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({ \
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typeof(op##_relaxed(args)) __ret = op##_relaxed(args); \
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smp_mb__after_atomic(); \
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__ret; \
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})
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#endif
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#ifndef __atomic_op_release
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#define __atomic_op_release(op, args...) \
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({ \
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smp_mb__before_atomic(); \
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op##_relaxed(args); \
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})
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#endif
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#ifndef __atomic_op_fence
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#define __atomic_op_fence(op, args...) \
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({ \
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typeof(op##_relaxed(args)) __ret; \
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smp_mb__before_atomic(); \
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__ret = op##_relaxed(args); \
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smp_mb__after_atomic(); \
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__ret; \
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})
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#endif
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/* atomic_add_return_relaxed */
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#ifndef atomic_add_return_relaxed
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#define atomic_add_return_relaxed atomic_add_return
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#define atomic_add_return_acquire atomic_add_return
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#define atomic_add_return_release atomic_add_return
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#else /* atomic_add_return_relaxed */
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#ifndef atomic_add_return_acquire
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#define atomic_add_return_acquire(...) \
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__atomic_op_acquire(atomic_add_return, __VA_ARGS__)
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#endif
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#ifndef atomic_add_return_release
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#define atomic_add_return_release(...) \
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__atomic_op_release(atomic_add_return, __VA_ARGS__)
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#endif
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#ifndef atomic_add_return
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#define atomic_add_return(...) \
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__atomic_op_fence(atomic_add_return, __VA_ARGS__)
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#endif
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#endif /* atomic_add_return_relaxed */
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/* atomic_inc_return_relaxed */
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#ifndef atomic_inc_return_relaxed
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#define atomic_inc_return_relaxed atomic_inc_return
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#define atomic_inc_return_acquire atomic_inc_return
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#define atomic_inc_return_release atomic_inc_return
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#else /* atomic_inc_return_relaxed */
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#ifndef atomic_inc_return_acquire
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#define atomic_inc_return_acquire(...) \
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__atomic_op_acquire(atomic_inc_return, __VA_ARGS__)
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#endif
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#ifndef atomic_inc_return_release
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#define atomic_inc_return_release(...) \
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__atomic_op_release(atomic_inc_return, __VA_ARGS__)
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#endif
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#ifndef atomic_inc_return
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#define atomic_inc_return(...) \
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__atomic_op_fence(atomic_inc_return, __VA_ARGS__)
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#endif
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#endif /* atomic_inc_return_relaxed */
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/* atomic_sub_return_relaxed */
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#ifndef atomic_sub_return_relaxed
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#define atomic_sub_return_relaxed atomic_sub_return
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#define atomic_sub_return_acquire atomic_sub_return
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#define atomic_sub_return_release atomic_sub_return
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#else /* atomic_sub_return_relaxed */
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#ifndef atomic_sub_return_acquire
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#define atomic_sub_return_acquire(...) \
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__atomic_op_acquire(atomic_sub_return, __VA_ARGS__)
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#endif
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#ifndef atomic_sub_return_release
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#define atomic_sub_return_release(...) \
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__atomic_op_release(atomic_sub_return, __VA_ARGS__)
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#endif
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#ifndef atomic_sub_return
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#define atomic_sub_return(...) \
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__atomic_op_fence(atomic_sub_return, __VA_ARGS__)
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#endif
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#endif /* atomic_sub_return_relaxed */
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/* atomic_dec_return_relaxed */
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#ifndef atomic_dec_return_relaxed
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#define atomic_dec_return_relaxed atomic_dec_return
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#define atomic_dec_return_acquire atomic_dec_return
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#define atomic_dec_return_release atomic_dec_return
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#else /* atomic_dec_return_relaxed */
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#ifndef atomic_dec_return_acquire
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#define atomic_dec_return_acquire(...) \
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__atomic_op_acquire(atomic_dec_return, __VA_ARGS__)
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#endif
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#ifndef atomic_dec_return_release
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#define atomic_dec_return_release(...) \
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__atomic_op_release(atomic_dec_return, __VA_ARGS__)
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#endif
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#ifndef atomic_dec_return
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#define atomic_dec_return(...) \
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__atomic_op_fence(atomic_dec_return, __VA_ARGS__)
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#endif
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#endif /* atomic_dec_return_relaxed */
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/* atomic_xchg_relaxed */
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#ifndef atomic_xchg_relaxed
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#define atomic_xchg_relaxed atomic_xchg
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#define atomic_xchg_acquire atomic_xchg
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#define atomic_xchg_release atomic_xchg
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#else /* atomic_xchg_relaxed */
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#ifndef atomic_xchg_acquire
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#define atomic_xchg_acquire(...) \
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__atomic_op_acquire(atomic_xchg, __VA_ARGS__)
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#endif
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#ifndef atomic_xchg_release
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#define atomic_xchg_release(...) \
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__atomic_op_release(atomic_xchg, __VA_ARGS__)
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#endif
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#ifndef atomic_xchg
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#define atomic_xchg(...) \
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__atomic_op_fence(atomic_xchg, __VA_ARGS__)
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#endif
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#endif /* atomic_xchg_relaxed */
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/* atomic_cmpxchg_relaxed */
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#ifndef atomic_cmpxchg_relaxed
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#define atomic_cmpxchg_relaxed atomic_cmpxchg
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#define atomic_cmpxchg_acquire atomic_cmpxchg
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#define atomic_cmpxchg_release atomic_cmpxchg
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#else /* atomic_cmpxchg_relaxed */
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#ifndef atomic_cmpxchg_acquire
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#define atomic_cmpxchg_acquire(...) \
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__atomic_op_acquire(atomic_cmpxchg, __VA_ARGS__)
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#endif
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#ifndef atomic_cmpxchg_release
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#define atomic_cmpxchg_release(...) \
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__atomic_op_release(atomic_cmpxchg, __VA_ARGS__)
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#endif
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#ifndef atomic_cmpxchg
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#define atomic_cmpxchg(...) \
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__atomic_op_fence(atomic_cmpxchg, __VA_ARGS__)
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#endif
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#endif /* atomic_cmpxchg_relaxed */
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#ifndef atomic64_read_acquire
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#define atomic64_read_acquire(v) smp_load_acquire(&(v)->counter)
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#endif
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#ifndef atomic64_set_release
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#define atomic64_set_release(v, i) smp_store_release(&(v)->counter, (i))
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#endif
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/* atomic64_add_return_relaxed */
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#ifndef atomic64_add_return_relaxed
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#define atomic64_add_return_relaxed atomic64_add_return
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#define atomic64_add_return_acquire atomic64_add_return
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#define atomic64_add_return_release atomic64_add_return
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#else /* atomic64_add_return_relaxed */
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#ifndef atomic64_add_return_acquire
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#define atomic64_add_return_acquire(...) \
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__atomic_op_acquire(atomic64_add_return, __VA_ARGS__)
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#endif
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#ifndef atomic64_add_return_release
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#define atomic64_add_return_release(...) \
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__atomic_op_release(atomic64_add_return, __VA_ARGS__)
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#endif
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#ifndef atomic64_add_return
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#define atomic64_add_return(...) \
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__atomic_op_fence(atomic64_add_return, __VA_ARGS__)
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#endif
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#endif /* atomic64_add_return_relaxed */
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/* atomic64_inc_return_relaxed */
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#ifndef atomic64_inc_return_relaxed
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#define atomic64_inc_return_relaxed atomic64_inc_return
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#define atomic64_inc_return_acquire atomic64_inc_return
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#define atomic64_inc_return_release atomic64_inc_return
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#else /* atomic64_inc_return_relaxed */
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#ifndef atomic64_inc_return_acquire
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#define atomic64_inc_return_acquire(...) \
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__atomic_op_acquire(atomic64_inc_return, __VA_ARGS__)
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#endif
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#ifndef atomic64_inc_return_release
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#define atomic64_inc_return_release(...) \
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__atomic_op_release(atomic64_inc_return, __VA_ARGS__)
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#endif
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#ifndef atomic64_inc_return
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#define atomic64_inc_return(...) \
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__atomic_op_fence(atomic64_inc_return, __VA_ARGS__)
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#endif
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#endif /* atomic64_inc_return_relaxed */
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/* atomic64_sub_return_relaxed */
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#ifndef atomic64_sub_return_relaxed
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#define atomic64_sub_return_relaxed atomic64_sub_return
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#define atomic64_sub_return_acquire atomic64_sub_return
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#define atomic64_sub_return_release atomic64_sub_return
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#else /* atomic64_sub_return_relaxed */
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#ifndef atomic64_sub_return_acquire
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#define atomic64_sub_return_acquire(...) \
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__atomic_op_acquire(atomic64_sub_return, __VA_ARGS__)
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#endif
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#ifndef atomic64_sub_return_release
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#define atomic64_sub_return_release(...) \
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__atomic_op_release(atomic64_sub_return, __VA_ARGS__)
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#endif
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#ifndef atomic64_sub_return
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#define atomic64_sub_return(...) \
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__atomic_op_fence(atomic64_sub_return, __VA_ARGS__)
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#endif
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#endif /* atomic64_sub_return_relaxed */
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/* atomic64_dec_return_relaxed */
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#ifndef atomic64_dec_return_relaxed
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#define atomic64_dec_return_relaxed atomic64_dec_return
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#define atomic64_dec_return_acquire atomic64_dec_return
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#define atomic64_dec_return_release atomic64_dec_return
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#else /* atomic64_dec_return_relaxed */
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#ifndef atomic64_dec_return_acquire
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#define atomic64_dec_return_acquire(...) \
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__atomic_op_acquire(atomic64_dec_return, __VA_ARGS__)
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#endif
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#ifndef atomic64_dec_return_release
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#define atomic64_dec_return_release(...) \
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__atomic_op_release(atomic64_dec_return, __VA_ARGS__)
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#endif
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#ifndef atomic64_dec_return
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#define atomic64_dec_return(...) \
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__atomic_op_fence(atomic64_dec_return, __VA_ARGS__)
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#endif
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#endif /* atomic64_dec_return_relaxed */
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/* atomic64_xchg_relaxed */
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#ifndef atomic64_xchg_relaxed
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#define atomic64_xchg_relaxed atomic64_xchg
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#define atomic64_xchg_acquire atomic64_xchg
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#define atomic64_xchg_release atomic64_xchg
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#else /* atomic64_xchg_relaxed */
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#ifndef atomic64_xchg_acquire
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#define atomic64_xchg_acquire(...) \
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__atomic_op_acquire(atomic64_xchg, __VA_ARGS__)
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#endif
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#ifndef atomic64_xchg_release
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#define atomic64_xchg_release(...) \
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__atomic_op_release(atomic64_xchg, __VA_ARGS__)
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#endif
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#ifndef atomic64_xchg
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#define atomic64_xchg(...) \
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__atomic_op_fence(atomic64_xchg, __VA_ARGS__)
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#endif
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#endif /* atomic64_xchg_relaxed */
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/* atomic64_cmpxchg_relaxed */
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#ifndef atomic64_cmpxchg_relaxed
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#define atomic64_cmpxchg_relaxed atomic64_cmpxchg
|
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#define atomic64_cmpxchg_acquire atomic64_cmpxchg
|
|
#define atomic64_cmpxchg_release atomic64_cmpxchg
|
|
|
|
#else /* atomic64_cmpxchg_relaxed */
|
|
|
|
#ifndef atomic64_cmpxchg_acquire
|
|
#define atomic64_cmpxchg_acquire(...) \
|
|
__atomic_op_acquire(atomic64_cmpxchg, __VA_ARGS__)
|
|
#endif
|
|
|
|
#ifndef atomic64_cmpxchg_release
|
|
#define atomic64_cmpxchg_release(...) \
|
|
__atomic_op_release(atomic64_cmpxchg, __VA_ARGS__)
|
|
#endif
|
|
|
|
#ifndef atomic64_cmpxchg
|
|
#define atomic64_cmpxchg(...) \
|
|
__atomic_op_fence(atomic64_cmpxchg, __VA_ARGS__)
|
|
#endif
|
|
#endif /* atomic64_cmpxchg_relaxed */
|
|
|
|
/* cmpxchg_relaxed */
|
|
#ifndef cmpxchg_relaxed
|
|
#define cmpxchg_relaxed cmpxchg
|
|
#define cmpxchg_acquire cmpxchg
|
|
#define cmpxchg_release cmpxchg
|
|
|
|
#else /* cmpxchg_relaxed */
|
|
|
|
#ifndef cmpxchg_acquire
|
|
#define cmpxchg_acquire(...) \
|
|
__atomic_op_acquire(cmpxchg, __VA_ARGS__)
|
|
#endif
|
|
|
|
#ifndef cmpxchg_release
|
|
#define cmpxchg_release(...) \
|
|
__atomic_op_release(cmpxchg, __VA_ARGS__)
|
|
#endif
|
|
|
|
#ifndef cmpxchg
|
|
#define cmpxchg(...) \
|
|
__atomic_op_fence(cmpxchg, __VA_ARGS__)
|
|
#endif
|
|
#endif /* cmpxchg_relaxed */
|
|
|
|
/* cmpxchg64_relaxed */
|
|
#ifndef cmpxchg64_relaxed
|
|
#define cmpxchg64_relaxed cmpxchg64
|
|
#define cmpxchg64_acquire cmpxchg64
|
|
#define cmpxchg64_release cmpxchg64
|
|
|
|
#else /* cmpxchg64_relaxed */
|
|
|
|
#ifndef cmpxchg64_acquire
|
|
#define cmpxchg64_acquire(...) \
|
|
__atomic_op_acquire(cmpxchg64, __VA_ARGS__)
|
|
#endif
|
|
|
|
#ifndef cmpxchg64_release
|
|
#define cmpxchg64_release(...) \
|
|
__atomic_op_release(cmpxchg64, __VA_ARGS__)
|
|
#endif
|
|
|
|
#ifndef cmpxchg64
|
|
#define cmpxchg64(...) \
|
|
__atomic_op_fence(cmpxchg64, __VA_ARGS__)
|
|
#endif
|
|
#endif /* cmpxchg64_relaxed */
|
|
|
|
/* xchg_relaxed */
|
|
#ifndef xchg_relaxed
|
|
#define xchg_relaxed xchg
|
|
#define xchg_acquire xchg
|
|
#define xchg_release xchg
|
|
|
|
#else /* xchg_relaxed */
|
|
|
|
#ifndef xchg_acquire
|
|
#define xchg_acquire(...) __atomic_op_acquire(xchg, __VA_ARGS__)
|
|
#endif
|
|
|
|
#ifndef xchg_release
|
|
#define xchg_release(...) __atomic_op_release(xchg, __VA_ARGS__)
|
|
#endif
|
|
|
|
#ifndef xchg
|
|
#define xchg(...) __atomic_op_fence(xchg, __VA_ARGS__)
|
|
#endif
|
|
#endif /* xchg_relaxed */
|
|
|
|
/**
|
|
* atomic_add_unless - add unless the number is already a given value
|
|
* @v: pointer of type atomic_t
|
|
* @a: the amount to add to v...
|
|
* @u: ...unless v is equal to u.
|
|
*
|
|
* Atomically adds @a to @v, so long as @v was not already @u.
|
|
* Returns non-zero if @v was not @u, and zero otherwise.
|
|
*/
|
|
static inline int atomic_add_unless(atomic_t *v, int a, int u)
|
|
{
|
|
return __atomic_add_unless(v, a, u) != u;
|
|
}
|
|
|
|
/**
|
|
* atomic_inc_not_zero - increment unless the number is zero
|
|
* @v: pointer of type atomic_t
|
|
*
|
|
* Atomically increments @v by 1, so long as @v is non-zero.
|
|
* Returns non-zero if @v was non-zero, and zero otherwise.
|
|
*/
|
|
#ifndef atomic_inc_not_zero
|
|
#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
|
|
#endif
|
|
|
|
#ifndef atomic_andnot
|
|
static inline void atomic_andnot(int i, atomic_t *v)
|
|
{
|
|
atomic_and(~i, v);
|
|
}
|
|
#endif
|
|
|
|
static inline __deprecated void atomic_clear_mask(unsigned int mask, atomic_t *v)
|
|
{
|
|
atomic_andnot(mask, v);
|
|
}
|
|
|
|
static inline __deprecated void atomic_set_mask(unsigned int mask, atomic_t *v)
|
|
{
|
|
atomic_or(mask, v);
|
|
}
|
|
|
|
/**
|
|
* atomic_inc_not_zero_hint - increment if not null
|
|
* @v: pointer of type atomic_t
|
|
* @hint: probable value of the atomic before the increment
|
|
*
|
|
* This version of atomic_inc_not_zero() gives a hint of probable
|
|
* value of the atomic. This helps processor to not read the memory
|
|
* before doing the atomic read/modify/write cycle, lowering
|
|
* number of bus transactions on some arches.
|
|
*
|
|
* Returns: 0 if increment was not done, 1 otherwise.
|
|
*/
|
|
#ifndef atomic_inc_not_zero_hint
|
|
static inline int atomic_inc_not_zero_hint(atomic_t *v, int hint)
|
|
{
|
|
int val, c = hint;
|
|
|
|
/* sanity test, should be removed by compiler if hint is a constant */
|
|
if (!hint)
|
|
return atomic_inc_not_zero(v);
|
|
|
|
do {
|
|
val = atomic_cmpxchg(v, c, c + 1);
|
|
if (val == c)
|
|
return 1;
|
|
c = val;
|
|
} while (c);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
#ifndef atomic_inc_unless_negative
|
|
static inline int atomic_inc_unless_negative(atomic_t *p)
|
|
{
|
|
int v, v1;
|
|
for (v = 0; v >= 0; v = v1) {
|
|
v1 = atomic_cmpxchg(p, v, v + 1);
|
|
if (likely(v1 == v))
|
|
return 1;
|
|
}
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
#ifndef atomic_dec_unless_positive
|
|
static inline int atomic_dec_unless_positive(atomic_t *p)
|
|
{
|
|
int v, v1;
|
|
for (v = 0; v <= 0; v = v1) {
|
|
v1 = atomic_cmpxchg(p, v, v - 1);
|
|
if (likely(v1 == v))
|
|
return 1;
|
|
}
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* atomic_dec_if_positive - decrement by 1 if old value positive
|
|
* @v: pointer of type atomic_t
|
|
*
|
|
* The function returns the old value of *v minus 1, even if
|
|
* the atomic variable, v, was not decremented.
|
|
*/
|
|
#ifndef atomic_dec_if_positive
|
|
static inline int atomic_dec_if_positive(atomic_t *v)
|
|
{
|
|
int c, old, dec;
|
|
c = atomic_read(v);
|
|
for (;;) {
|
|
dec = c - 1;
|
|
if (unlikely(dec < 0))
|
|
break;
|
|
old = atomic_cmpxchg((v), c, dec);
|
|
if (likely(old == c))
|
|
break;
|
|
c = old;
|
|
}
|
|
return dec;
|
|
}
|
|
#endif
|
|
|
|
/**
|
|
* fetch_or - perform *ptr |= mask and return old value of *ptr
|
|
* @ptr: pointer to value
|
|
* @mask: mask to OR on the value
|
|
*
|
|
* cmpxchg based fetch_or, macro so it works for different integer types
|
|
*/
|
|
#ifndef fetch_or
|
|
#define fetch_or(ptr, mask) \
|
|
({ typeof(*(ptr)) __old, __val = *(ptr); \
|
|
for (;;) { \
|
|
__old = cmpxchg((ptr), __val, __val | (mask)); \
|
|
if (__old == __val) \
|
|
break; \
|
|
__val = __old; \
|
|
} \
|
|
__old; \
|
|
})
|
|
#endif
|
|
|
|
|
|
#ifdef CONFIG_GENERIC_ATOMIC64
|
|
#include <asm-generic/atomic64.h>
|
|
#endif
|
|
|
|
#ifndef atomic64_andnot
|
|
static inline void atomic64_andnot(long long i, atomic64_t *v)
|
|
{
|
|
atomic64_and(~i, v);
|
|
}
|
|
#endif
|
|
|
|
#include <asm-generic/atomic-long.h>
|
|
|
|
#endif /* _LINUX_ATOMIC_H */
|