forked from mirrors/linux
fda8d26e61
Based on 1 normalized pattern(s): licensed under the gpl 2 extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 135 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Reviewed-by: Steve Winslow <swinslow@gmail.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190528170026.071193225@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
127 lines
4.4 KiB
C
127 lines
4.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* ADF4350/ADF4351 SPI PLL driver
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*
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* Copyright 2012-2013 Analog Devices Inc.
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*/
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#ifndef IIO_PLL_ADF4350_H_
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#define IIO_PLL_ADF4350_H_
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/* Registers */
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#define ADF4350_REG0 0
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#define ADF4350_REG1 1
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#define ADF4350_REG2 2
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#define ADF4350_REG3 3
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#define ADF4350_REG4 4
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#define ADF4350_REG5 5
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/* REG0 Bit Definitions */
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#define ADF4350_REG0_FRACT(x) (((x) & 0xFFF) << 3)
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#define ADF4350_REG0_INT(x) (((x) & 0xFFFF) << 15)
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/* REG1 Bit Definitions */
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#define ADF4350_REG1_MOD(x) (((x) & 0xFFF) << 3)
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#define ADF4350_REG1_PHASE(x) (((x) & 0xFFF) << 15)
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#define ADF4350_REG1_PRESCALER (1 << 27)
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/* REG2 Bit Definitions */
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#define ADF4350_REG2_COUNTER_RESET_EN (1 << 3)
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#define ADF4350_REG2_CP_THREESTATE_EN (1 << 4)
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#define ADF4350_REG2_POWER_DOWN_EN (1 << 5)
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#define ADF4350_REG2_PD_POLARITY_POS (1 << 6)
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#define ADF4350_REG2_LDP_6ns (1 << 7)
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#define ADF4350_REG2_LDP_10ns (0 << 7)
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#define ADF4350_REG2_LDF_FRACT_N (0 << 8)
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#define ADF4350_REG2_LDF_INT_N (1 << 8)
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#define ADF4350_REG2_CHARGE_PUMP_CURR_uA(x) (((((x)-312) / 312) & 0xF) << 9)
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#define ADF4350_REG2_DOUBLE_BUFF_EN (1 << 13)
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#define ADF4350_REG2_10BIT_R_CNT(x) ((x) << 14)
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#define ADF4350_REG2_RDIV2_EN (1 << 24)
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#define ADF4350_REG2_RMULT2_EN (1 << 25)
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#define ADF4350_REG2_MUXOUT(x) ((x) << 26)
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#define ADF4350_REG2_NOISE_MODE(x) (((unsigned)(x)) << 29)
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#define ADF4350_MUXOUT_THREESTATE 0
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#define ADF4350_MUXOUT_DVDD 1
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#define ADF4350_MUXOUT_GND 2
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#define ADF4350_MUXOUT_R_DIV_OUT 3
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#define ADF4350_MUXOUT_N_DIV_OUT 4
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#define ADF4350_MUXOUT_ANALOG_LOCK_DETECT 5
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#define ADF4350_MUXOUT_DIGITAL_LOCK_DETECT 6
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/* REG3 Bit Definitions */
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#define ADF4350_REG3_12BIT_CLKDIV(x) ((x) << 3)
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#define ADF4350_REG3_12BIT_CLKDIV_MODE(x) ((x) << 16)
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#define ADF4350_REG3_12BIT_CSR_EN (1 << 18)
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#define ADF4351_REG3_CHARGE_CANCELLATION_EN (1 << 21)
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#define ADF4351_REG3_ANTI_BACKLASH_3ns_EN (1 << 22)
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#define ADF4351_REG3_BAND_SEL_CLOCK_MODE_HIGH (1 << 23)
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/* REG4 Bit Definitions */
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#define ADF4350_REG4_OUTPUT_PWR(x) ((x) << 3)
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#define ADF4350_REG4_RF_OUT_EN (1 << 5)
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#define ADF4350_REG4_AUX_OUTPUT_PWR(x) ((x) << 6)
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#define ADF4350_REG4_AUX_OUTPUT_EN (1 << 8)
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#define ADF4350_REG4_AUX_OUTPUT_FUND (1 << 9)
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#define ADF4350_REG4_AUX_OUTPUT_DIV (0 << 9)
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#define ADF4350_REG4_MUTE_TILL_LOCK_EN (1 << 10)
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#define ADF4350_REG4_VCO_PWRDOWN_EN (1 << 11)
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#define ADF4350_REG4_8BIT_BAND_SEL_CLKDIV(x) ((x) << 12)
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#define ADF4350_REG4_RF_DIV_SEL(x) ((x) << 20)
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#define ADF4350_REG4_FEEDBACK_DIVIDED (0 << 23)
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#define ADF4350_REG4_FEEDBACK_FUND (1 << 23)
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/* REG5 Bit Definitions */
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#define ADF4350_REG5_LD_PIN_MODE_LOW (0 << 22)
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#define ADF4350_REG5_LD_PIN_MODE_DIGITAL (1 << 22)
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#define ADF4350_REG5_LD_PIN_MODE_HIGH (3 << 22)
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/* Specifications */
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#define ADF4350_MAX_OUT_FREQ 4400000000ULL /* Hz */
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#define ADF4350_MIN_OUT_FREQ 137500000 /* Hz */
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#define ADF4351_MIN_OUT_FREQ 34375000 /* Hz */
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#define ADF4350_MIN_VCO_FREQ 2200000000ULL /* Hz */
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#define ADF4350_MAX_FREQ_45_PRESC 3000000000ULL /* Hz */
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#define ADF4350_MAX_FREQ_PFD 32000000 /* Hz */
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#define ADF4350_MAX_BANDSEL_CLK 125000 /* Hz */
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#define ADF4350_MAX_FREQ_REFIN 250000000 /* Hz */
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#define ADF4350_MAX_MODULUS 4095
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#define ADF4350_MAX_R_CNT 1023
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/**
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* struct adf4350_platform_data - platform specific information
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* @name: Optional device name.
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* @clkin: REFin frequency in Hz.
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* @channel_spacing: Channel spacing in Hz (influences MODULUS).
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* @power_up_frequency: Optional, If set in Hz the PLL tunes to the desired
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* frequency on probe.
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* @ref_div_factor: Optional, if set the driver skips dynamic calculation
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* and uses this default value instead.
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* @ref_doubler_en: Enables reference doubler.
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* @ref_div2_en: Enables reference divider.
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* @r2_user_settings: User defined settings for ADF4350/1 REGISTER_2.
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* @r3_user_settings: User defined settings for ADF4350/1 REGISTER_3.
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* @r4_user_settings: User defined settings for ADF4350/1 REGISTER_4.
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* @gpio_lock_detect: Optional, if set with a valid GPIO number,
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* pll lock state is tested upon read.
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* If not used - set to -1.
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*/
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struct adf4350_platform_data {
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char name[32];
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unsigned long clkin;
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unsigned long channel_spacing;
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unsigned long long power_up_frequency;
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unsigned short ref_div_factor; /* 10-bit R counter */
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bool ref_doubler_en;
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bool ref_div2_en;
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unsigned r2_user_settings;
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unsigned r3_user_settings;
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unsigned r4_user_settings;
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int gpio_lock_detect;
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};
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#endif /* IIO_PLL_ADF4350_H_ */
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