forked from mirrors/linux
ec8ca8a348
The split into multiple structures of the "ll" register bank is impractical. It makes it hard to add ll_lfps_timers_2 which is at offset 0x794, which is outside of the existing "lfps" structure and would require us to add yet another one. Instead, move all the "ll" registers into a single usb338x_ll_regs structure, and add ll_lfps_timers_2 while at it. It will be used in a subsequent patch. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
219 lines
7.8 KiB
C
219 lines
7.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* USB 338x super/high/full speed USB device controller.
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* Unlike many such controllers, this one talks PCI.
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*
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* Copyright (C) 2002 NetChip Technology, Inc. (http://www.netchip.com)
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* Copyright (C) 2003 David Brownell
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* Copyright (C) 2014 Ricardo Ribalda - Qtechnology/AS
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __LINUX_USB_USB338X_H
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#define __LINUX_USB_USB338X_H
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#include <linux/usb/net2280.h>
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/*
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* Extra defined bits for net2280 registers
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*/
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#define SCRATCH 0x0b
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#define DEFECT7374_FSM_FIELD 28
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#define SUPER_SPEED 8
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#define DMA_REQUEST_OUTSTANDING 5
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#define DMA_PAUSE_DONE_INTERRUPT 26
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#define SET_ISOCHRONOUS_DELAY 24
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#define SET_SEL 22
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#define SUPER_SPEED_MODE 8
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/*ep_cfg*/
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#define MAX_BURST_SIZE 24
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#define EP_FIFO_BYTE_COUNT 16
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#define IN_ENDPOINT_ENABLE 14
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#define IN_ENDPOINT_TYPE 12
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#define OUT_ENDPOINT_ENABLE 10
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#define OUT_ENDPOINT_TYPE 8
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#define USB3380_EP_CFG_MASK_IN ((0x3 << IN_ENDPOINT_TYPE) | \
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BIT(IN_ENDPOINT_ENABLE))
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#define USB3380_EP_CFG_MASK_OUT ((0x3 << OUT_ENDPOINT_TYPE) | \
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BIT(OUT_ENDPOINT_ENABLE))
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struct usb338x_usb_ext_regs {
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u32 usbclass;
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#define DEVICE_PROTOCOL 16
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#define DEVICE_SUB_CLASS 8
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#define DEVICE_CLASS 0
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u32 ss_sel;
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#define U2_SYSTEM_EXIT_LATENCY 8
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#define U1_SYSTEM_EXIT_LATENCY 0
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u32 ss_del;
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#define U2_DEVICE_EXIT_LATENCY 8
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#define U1_DEVICE_EXIT_LATENCY 0
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u32 usb2lpm;
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#define USB_L1_LPM_HIRD 2
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#define USB_L1_LPM_REMOTE_WAKE 1
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#define USB_L1_LPM_SUPPORT 0
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u32 usb3belt;
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#define BELT_MULTIPLIER 10
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#define BEST_EFFORT_LATENCY_TOLERANCE 0
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u32 usbctl2;
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#define LTM_ENABLE 7
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#define U2_ENABLE 6
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#define U1_ENABLE 5
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#define FUNCTION_SUSPEND 4
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#define USB3_CORE_ENABLE 3
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#define USB2_CORE_ENABLE 2
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#define SERIAL_NUMBER_STRING_ENABLE 0
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u32 in_timeout;
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#define GPEP3_TIMEOUT 19
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#define GPEP2_TIMEOUT 18
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#define GPEP1_TIMEOUT 17
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#define GPEP0_TIMEOUT 16
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#define GPEP3_TIMEOUT_VALUE 13
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#define GPEP3_TIMEOUT_ENABLE 12
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#define GPEP2_TIMEOUT_VALUE 9
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#define GPEP2_TIMEOUT_ENABLE 8
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#define GPEP1_TIMEOUT_VALUE 5
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#define GPEP1_TIMEOUT_ENABLE 4
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#define GPEP0_TIMEOUT_VALUE 1
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#define GPEP0_TIMEOUT_ENABLE 0
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u32 isodelay;
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#define ISOCHRONOUS_DELAY 0
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} __packed;
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struct usb338x_fifo_regs {
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/* offset 0x0500, 0x0520, 0x0540, 0x0560, 0x0580 */
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u32 ep_fifo_size_base;
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#define IN_FIFO_BASE_ADDRESS 22
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#define IN_FIFO_SIZE 16
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#define OUT_FIFO_BASE_ADDRESS 6
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#define OUT_FIFO_SIZE 0
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u32 ep_fifo_out_wrptr;
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u32 ep_fifo_out_rdptr;
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u32 ep_fifo_in_wrptr;
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u32 ep_fifo_in_rdptr;
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u32 unused[3];
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} __packed;
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/* Link layer */
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struct usb338x_ll_regs {
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/* offset 0x700 */
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u32 ll_ltssm_ctrl1;
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u32 ll_ltssm_ctrl2;
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u32 ll_ltssm_ctrl3;
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u32 unused1;
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/* 0x710 */
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u32 unused2;
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u32 ll_general_ctrl0;
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u32 ll_general_ctrl1;
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#define PM_U3_AUTO_EXIT 29
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#define PM_U2_AUTO_EXIT 28
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#define PM_U1_AUTO_EXIT 27
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#define PM_FORCE_U2_ENTRY 26
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#define PM_FORCE_U1_ENTRY 25
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#define PM_LGO_COLLISION_SEND_LAU 24
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#define PM_DIR_LINK_REJECT 23
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#define PM_FORCE_LINK_ACCEPT 22
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#define PM_DIR_ENTRY_U3 20
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#define PM_DIR_ENTRY_U2 19
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#define PM_DIR_ENTRY_U1 18
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#define PM_U2_ENABLE 17
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#define PM_U1_ENABLE 16
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#define SKP_THRESHOLD_ADJUST_FMW 8
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#define RESEND_DPP_ON_LRTY_FMW 7
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#define DL_BIT_VALUE_FMW 6
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#define FORCE_DL_BIT 5
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u32 ll_general_ctrl2;
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#define SELECT_INVERT_LANE_POLARITY 7
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#define FORCE_INVERT_LANE_POLARITY 6
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/* 0x720 */
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u32 ll_general_ctrl3;
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u32 ll_general_ctrl4;
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u32 ll_error_gen;
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u32 unused3;
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/* 0x730 */
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u32 unused4[4];
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/* 0x740 */
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u32 unused5[2];
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u32 ll_lfps_5;
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#define TIMER_LFPS_6US 16
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u32 ll_lfps_6;
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#define TIMER_LFPS_80US 0
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/* 0x750 */
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u32 unused6[8];
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/* 0x770 */
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u32 unused7[3];
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u32 ll_tsn_counters_2;
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#define HOT_TX_NORESET_TS2 24
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/* 0x780 */
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u32 ll_tsn_counters_3;
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#define HOT_RX_RESET_TS2 0
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u32 unused8[3];
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/* 0x790 */
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u32 unused9;
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u32 ll_lfps_timers_2;
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#define LFPS_TIMERS_2_WORKAROUND_VALUE 0x084d
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u32 unused10;
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u32 ll_tsn_chicken_bit;
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#define RECOVERY_IDLE_TO_RECOVER_FMW 3
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} __packed;
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/* protocol layer */
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struct usb338x_pl_regs {
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/* offset 0x800 */
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u32 pl_reg_1;
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u32 pl_reg_2;
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u32 pl_reg_3;
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u32 pl_reg_4;
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u32 pl_ep_ctrl;
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/* Protocol Layer Endpoint Control*/
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#define PL_EP_CTRL 0x810
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#define ENDPOINT_SELECT 0
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/* [4:0] */
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#define EP_INITIALIZED 16
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#define SEQUENCE_NUMBER_RESET 17
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#define CLEAR_ACK_ERROR_CODE 20
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u32 pl_reg_6;
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u32 pl_reg_7;
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u32 pl_reg_8;
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u32 pl_ep_status_1;
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/* Protocol Layer Endpoint Status 1*/
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#define PL_EP_STATUS_1 0x820
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#define STATE 16
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#define ACK_GOOD_NORMAL 0x11
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#define ACK_GOOD_MORE_ACKS_TO_COME 0x16
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u32 pl_ep_status_2;
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u32 pl_ep_status_3;
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/* Protocol Layer Endpoint Status 3*/
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#define PL_EP_STATUS_3 0x828
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#define SEQUENCE_NUMBER 0
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u32 pl_ep_status_4;
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/* Protocol Layer Endpoint Status 4*/
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#define PL_EP_STATUS_4 0x82c
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u32 pl_ep_cfg_4;
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/* Protocol Layer Endpoint Configuration 4*/
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#define PL_EP_CFG_4 0x830
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#define NON_CTRL_IN_TOLERATE_BAD_DIR 6
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} __packed;
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#endif /* __LINUX_USB_USB338X_H */
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