forked from mirrors/linux
		
	 00eb3630a9
			
		
	
	
		00eb3630a9
		
	
	
	
	
		
			
			Since commit b36581df7e ("spi: imx: Using existing properties for
chipselects") the device tree property 'fsl,spi-num-chipselects' is
unused and it is already marked as obsolete in device tree binding
documentation. Remove the property from the existing DTS files to
avoid its reoccurence on copying.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
		
	
			
		
			
				
	
	
		
			262 lines
		
	
	
	
		
			5.5 KiB
		
	
	
	
		
			Text
		
	
	
	
	
	
			
		
		
	
	
			262 lines
		
	
	
	
		
			5.5 KiB
		
	
	
	
		
			Text
		
	
	
	
	
	
| /*
 | |
|  * Copyright 2013 Armadeus Systems - <support@armadeus.com>
 | |
|  *
 | |
|  * The code contained herein is licensed under the GNU General Public
 | |
|  * License. You may obtain a copy of the GNU General Public License
 | |
|  * Version 2 or later at the following locations:
 | |
|  *
 | |
|  * http://www.opensource.org/licenses/gpl-license.html
 | |
|  * http://www.gnu.org/copyleft/gpl.html
 | |
|  */
 | |
| 
 | |
| /* APF27Dev is a docking board for the APF27 SOM */
 | |
| #include "imx27-apf27.dts"
 | |
| 
 | |
| / {
 | |
| 	model = "Armadeus Systems APF27Dev docking/development board";
 | |
| 	compatible = "armadeus,imx27-apf27dev", "armadeus,imx27-apf27", "fsl,imx27";
 | |
| 
 | |
| 	display: display {
 | |
| 		model = "Chimei-LW700AT9003";
 | |
| 		native-mode = <&timing0>;
 | |
| 		bits-per-pixel = <16>;  /* non-standard but required */
 | |
| 		fsl,pcr = <0xfae80083>;	/* non-standard but required */
 | |
| 		display-timings {
 | |
| 			timing0: 800x480 {
 | |
| 				clock-frequency = <33000033>;
 | |
| 				hactive = <800>;
 | |
| 				vactive = <480>;
 | |
| 				hback-porch = <96>;
 | |
| 				hfront-porch = <96>;
 | |
| 				vback-porch = <20>;
 | |
| 				vfront-porch = <21>;
 | |
| 				hsync-len = <64>;
 | |
| 				vsync-len = <4>;
 | |
| 			};
 | |
| 		};
 | |
| 	};
 | |
| 
 | |
| 	gpio-keys {
 | |
| 		compatible = "gpio-keys";
 | |
| 		pinctrl-names = "default";
 | |
| 		pinctrl-0 = <&pinctrl_gpio_keys>;
 | |
| 
 | |
| 		user-key {
 | |
| 			label = "user";
 | |
| 			gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>;
 | |
| 			linux,code = <276>; /* BTN_EXTRA */
 | |
| 		};
 | |
| 	};
 | |
| 
 | |
| 	leds {
 | |
| 		compatible = "gpio-leds";
 | |
| 		pinctrl-names = "default";
 | |
| 		pinctrl-0 = <&pinctrl_gpio_leds>;
 | |
| 
 | |
| 		user {
 | |
| 			label = "Heartbeat";
 | |
| 			gpios = <&gpio6 14 GPIO_ACTIVE_HIGH>;
 | |
| 			linux,default-trigger = "heartbeat";
 | |
| 		};
 | |
| 	};
 | |
| 
 | |
| 	regulators {
 | |
| 		compatible = "simple-bus";
 | |
| 		#address-cells = <1>;
 | |
| 		#size-cells = <0>;
 | |
| 
 | |
| 		reg_max5821: regulator@0 {
 | |
| 			compatible = "regulator-fixed";
 | |
| 			reg = <0>;
 | |
| 			regulator-name = "max5821-reg";
 | |
| 			regulator-min-microvolt = <2500000>;
 | |
| 			regulator-max-microvolt = <2500000>;
 | |
| 			regulator-always-on;
 | |
| 		};
 | |
| 	};
 | |
| };
 | |
| 
 | |
| &cspi1 {
 | |
| 	cs-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
 | |
| 	pinctrl-names = "default";
 | |
| 	pinctrl-0 = <&pinctrl_cspi1 &pinctrl_cspi1_cs>;
 | |
| 	status = "okay";
 | |
| 
 | |
| 	adc@0 {
 | |
| 		compatible = "maxim,max1027";
 | |
| 		reg = <0>;
 | |
| 		interrupt-parent = <&gpio5>;
 | |
| 		interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
 | |
| 		pinctrl-names = "default";
 | |
| 		pinctrl-0 = <&pinctrl_max1027>;
 | |
| 		spi-max-frequency = <10000000>;
 | |
| 	};
 | |
| };
 | |
| 
 | |
| &cspi2 {
 | |
| 	cs-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>,
 | |
| 		   <&gpio4 27 GPIO_ACTIVE_LOW>,
 | |
| 		   <&gpio2 17 GPIO_ACTIVE_LOW>;
 | |
| 	pinctrl-names = "default";
 | |
| 	pinctrl-0 = <&pinctrl_cspi2 &pinctrl_cspi2_cs>;
 | |
| 	status = "okay";
 | |
| };
 | |
| 
 | |
| &fb {
 | |
| 	display = <&display>;
 | |
| 	fsl,dmacr = <0x00020010>;
 | |
| 	pinctrl-names = "default";
 | |
| 	pinctrl-0 = <&pinctrl_imxfb1>;
 | |
| 	status = "okay";
 | |
| };
 | |
| 
 | |
| &i2c1 {
 | |
| 	clock-frequency = <400000>;
 | |
| 	pinctrl-names = "default";
 | |
| 	pinctrl-0 = <&pinctrl_i2c1>;
 | |
| 	status = "okay";
 | |
| 
 | |
| 	rtc@68 {
 | |
| 		compatible = "dallas,ds1374";
 | |
| 		reg = <0x68>;
 | |
| 	};
 | |
| 
 | |
| 	max5821@38 {
 | |
| 		compatible = "maxim,max5821";
 | |
| 		reg = <0x38>;
 | |
| 		vref-supply = <®_max5821>;
 | |
| 	};
 | |
| };
 | |
| 
 | |
| &i2c2 {
 | |
| 	pinctrl-names = "default";
 | |
| 	pinctrl-0 = <&pinctrl_i2c2>;
 | |
| 	status = "okay";
 | |
| };
 | |
| 
 | |
| &iomuxc {
 | |
| 	imx27-apf27dev {
 | |
| 		pinctrl_cspi1: cspi1grp {
 | |
| 			fsl,pins = <
 | |
| 				MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0
 | |
| 				MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0
 | |
| 				MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0
 | |
| 			>;
 | |
| 		};
 | |
| 
 | |
| 		pinctrl_cspi1_cs: cspi1csgrp {
 | |
| 			fsl,pins = <MX27_PAD_CSPI1_SS0__GPIO4_28 0x0>;
 | |
| 		};
 | |
| 
 | |
| 		pinctrl_cspi2: cspi2grp {
 | |
| 			fsl,pins = <
 | |
| 				MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x0
 | |
| 				MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x0
 | |
| 				MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x0
 | |
| 			>;
 | |
| 		};
 | |
| 
 | |
| 		pinctrl_cspi2_cs: cspi2csgrp {
 | |
| 			fsl,pins = <
 | |
| 				MX27_PAD_CSI_D5__GPIO2_17 0x0
 | |
| 				MX27_PAD_CSPI2_SS0__GPIO4_21 0x0
 | |
| 				MX27_PAD_CSPI1_SS1__GPIO4_27 0x0
 | |
| 			>;
 | |
| 		};
 | |
| 
 | |
| 		pinctrl_gpio_leds: gpioledsgrp {
 | |
| 			fsl,pins = <MX27_PAD_PC_VS1__GPIO6_14 0x0>;
 | |
| 		};
 | |
| 
 | |
| 		pinctrl_gpio_keys: gpiokeysgrp {
 | |
| 			fsl,pins = <MX27_PAD_PC_VS2__GPIO6_13 0x0>;
 | |
| 		};
 | |
| 
 | |
| 		pinctrl_imxfb1: imxfbgrp {
 | |
| 			fsl,pins = <
 | |
| 				MX27_PAD_CLS__CLS 0x0
 | |
| 				MX27_PAD_CONTRAST__CONTRAST 0x0
 | |
| 				MX27_PAD_LD0__LD0 0x0
 | |
| 				MX27_PAD_LD1__LD1 0x0
 | |
| 				MX27_PAD_LD2__LD2 0x0
 | |
| 				MX27_PAD_LD3__LD3 0x0
 | |
| 				MX27_PAD_LD4__LD4 0x0
 | |
| 				MX27_PAD_LD5__LD5 0x0
 | |
| 				MX27_PAD_LD6__LD6 0x0
 | |
| 				MX27_PAD_LD7__LD7 0x0
 | |
| 				MX27_PAD_LD8__LD8 0x0
 | |
| 				MX27_PAD_LD9__LD9 0x0
 | |
| 				MX27_PAD_LD10__LD10 0x0
 | |
| 				MX27_PAD_LD11__LD11 0x0
 | |
| 				MX27_PAD_LD12__LD12 0x0
 | |
| 				MX27_PAD_LD13__LD13 0x0
 | |
| 				MX27_PAD_LD14__LD14 0x0
 | |
| 				MX27_PAD_LD15__LD15 0x0
 | |
| 				MX27_PAD_LD16__LD16 0x0
 | |
| 				MX27_PAD_LD17__LD17 0x0
 | |
| 				MX27_PAD_LSCLK__LSCLK 0x0
 | |
| 				MX27_PAD_OE_ACD__OE_ACD 0x0
 | |
| 				MX27_PAD_PS__PS 0x0
 | |
| 				MX27_PAD_REV__REV 0x0
 | |
| 				MX27_PAD_SPL_SPR__SPL_SPR 0x0
 | |
| 				MX27_PAD_HSYNC__HSYNC 0x0
 | |
| 				MX27_PAD_VSYNC__VSYNC 0x0
 | |
| 			>;
 | |
| 		};
 | |
| 
 | |
| 		pinctrl_i2c1: i2c1grp {
 | |
| 			fsl,pins = <
 | |
| 				MX27_PAD_I2C_DATA__I2C_DATA 0x0
 | |
| 				MX27_PAD_I2C_CLK__I2C_CLK 0x0
 | |
| 			>;
 | |
| 		};
 | |
| 
 | |
| 		pinctrl_i2c2: i2c2grp {
 | |
| 			fsl,pins = <
 | |
| 				MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
 | |
| 				MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
 | |
| 			>;
 | |
| 		};
 | |
| 
 | |
| 		pinctrl_max1027: max1027 {
 | |
| 			 fsl,pins = <
 | |
| 				 MX27_PAD_UART1_CTS__GPIO5_14 0x0 /* CNVST */
 | |
| 				 MX27_PAD_UART1_RTS__GPIO5_15 0x0 /* EOC */
 | |
| 			>;
 | |
| 		};
 | |
| 
 | |
| 		pinctrl_pwm: pwmgrp {
 | |
| 			fsl,pins = <
 | |
| 				MX27_PAD_PWMO__PWMO 0x0
 | |
| 			>;
 | |
| 		};
 | |
| 
 | |
| 		pinctrl_sdhc2: sdhc2grp {
 | |
| 			fsl,pins = <
 | |
| 				MX27_PAD_SD2_CLK__SD2_CLK 0x0
 | |
| 				MX27_PAD_SD2_CMD__SD2_CMD 0x0
 | |
| 				MX27_PAD_SD2_D0__SD2_D0 0x0
 | |
| 				MX27_PAD_SD2_D1__SD2_D1 0x0
 | |
| 				MX27_PAD_SD2_D2__SD2_D2 0x0
 | |
| 				MX27_PAD_SD2_D3__SD2_D3 0x0
 | |
| 			>;
 | |
| 		};
 | |
| 
 | |
| 		pinctrl_sdhc2_cd: sdhc2cdgrp {
 | |
| 			fsl,pins = <MX27_PAD_TOUT__GPIO3_14 0x0>;
 | |
| 		};
 | |
| 	};
 | |
| };
 | |
| 
 | |
| &sdhci2 {
 | |
| 	bus-width = <4>;
 | |
| 	cd-gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
 | |
| 	pinctrl-names = "default";
 | |
| 	pinctrl-0 = <&pinctrl_sdhc2 &pinctrl_sdhc2_cd>;
 | |
| 	status = "okay";
 | |
| };
 | |
| 
 | |
| &pwm {
 | |
| 	pinctrl-names = "default";
 | |
| 	pinctrl-0 = <&pinctrl_pwm>;
 | |
| };
 |