forked from mirrors/linux
dc413a90ed
Various driver updates for platforms and a couple of the small driver
subsystems we merge through our tree:
Among the larger pieces:
- Power management improvements for TI am335x and am437x (RTC suspend/wake)
- Misc new additions for Amlogic (socinfo updates)
- ZynqMP FPGA manager
- Nvidia improvements for reset/powergate handling
- PMIC wrapper for Mediatek MT8516
- Misc fixes/improvements for ARM SCMI, TEE, NXP i.MX SCU drivers
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Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC-related driver updates from Olof Johansson:
"Various driver updates for platforms and a couple of the small driver
subsystems we merge through our tree:
Among the larger pieces:
- Power management improvements for TI am335x and am437x (RTC
suspend/wake)
- Misc new additions for Amlogic (socinfo updates)
- ZynqMP FPGA manager
- Nvidia improvements for reset/powergate handling
- PMIC wrapper for Mediatek MT8516
- Misc fixes/improvements for ARM SCMI, TEE, NXP i.MX SCU drivers"
* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (57 commits)
soc: aspeed: fix Kconfig
soc: add aspeed folder and misc drivers
spi: zynqmp: Fix build break
soc: imx: Add generic i.MX8 SoC driver
MAINTAINERS: Update email for Qualcomm SoC maintainer
memory: tegra: Fix a typos for "fdcdwr2" mc client
Revert "ARM: tegra: Restore memory arbitration on resume from LP1 on Tegra30+"
memory: tegra: Replace readl-writel with mc_readl-mc_writel
memory: tegra: Fix integer overflow on tick value calculation
memory: tegra: Fix missed registers values latching
ARM: tegra: cpuidle: Handle tick broadcasting within cpuidle core on Tegra20/30
optee: allow to work without static shared memory
soc/tegra: pmc: Move powergate initialisation to probe
soc/tegra: pmc: Remove reset sysfs entries on error
soc/tegra: pmc: Fix reset sources and levels
soc: amlogic: meson-gx-pwrc-vpu: Add support for G12A
soc: amlogic: meson-gx-pwrc-vpu: Fix power on/off register bitmask
fpga manager: Adding FPGA Manager support for Xilinx zynqmp
dt-bindings: fpga: Add bindings for ZynqMP fpga driver
firmware: xilinx: Add fpga API's
...
138 lines
3.8 KiB
C
138 lines
3.8 KiB
C
/*
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* Copyright (C) 2010 Google, Inc.
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*
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* Author:
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* Colin Cross <ccross@google.com>
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* Erik Gilling <konkers@google.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __MACH_TEGRA_IOMAP_H
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#define __MACH_TEGRA_IOMAP_H
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#include <asm/pgtable.h>
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#include <linux/sizes.h>
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#define TEGRA_IRAM_BASE 0x40000000
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#define TEGRA_IRAM_SIZE SZ_256K
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#define TEGRA_ARM_PERIF_BASE 0x50040000
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#define TEGRA_ARM_PERIF_SIZE SZ_8K
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#define TEGRA_ARM_INT_DIST_BASE 0x50041000
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#define TEGRA_ARM_INT_DIST_SIZE SZ_4K
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#define TEGRA_TMR1_BASE 0x60005000
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#define TEGRA_TMR1_SIZE SZ_8
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#define TEGRA_TMR2_BASE 0x60005008
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#define TEGRA_TMR2_SIZE SZ_8
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#define TEGRA_TMRUS_BASE 0x60005010
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#define TEGRA_TMRUS_SIZE SZ_64
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#define TEGRA_TMR3_BASE 0x60005050
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#define TEGRA_TMR3_SIZE SZ_8
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#define TEGRA_TMR4_BASE 0x60005058
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#define TEGRA_TMR4_SIZE SZ_8
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#define TEGRA_CLK_RESET_BASE 0x60006000
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#define TEGRA_CLK_RESET_SIZE SZ_4K
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#define TEGRA_FLOW_CTRL_BASE 0x60007000
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#define TEGRA_FLOW_CTRL_SIZE 20
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#define TEGRA_SB_BASE 0x6000C200
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#define TEGRA_SB_SIZE 256
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#define TEGRA_EXCEPTION_VECTORS_BASE 0x6000F000
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#define TEGRA_EXCEPTION_VECTORS_SIZE SZ_4K
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#define TEGRA_APB_MISC_BASE 0x70000000
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#define TEGRA_APB_MISC_SIZE SZ_4K
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#define TEGRA_UARTA_BASE 0x70006000
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#define TEGRA_UARTA_SIZE SZ_64
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#define TEGRA_UARTB_BASE 0x70006040
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#define TEGRA_UARTB_SIZE SZ_64
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#define TEGRA_UARTC_BASE 0x70006200
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#define TEGRA_UARTC_SIZE SZ_256
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#define TEGRA_UARTD_BASE 0x70006300
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#define TEGRA_UARTD_SIZE SZ_256
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#define TEGRA_UARTE_BASE 0x70006400
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#define TEGRA_UARTE_SIZE SZ_256
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#define TEGRA_PMC_BASE 0x7000E400
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#define TEGRA_PMC_SIZE SZ_256
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#define TEGRA_EMC_BASE 0x7000F400
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#define TEGRA_EMC_SIZE SZ_1K
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#define TEGRA_EMC0_BASE 0x7001A000
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#define TEGRA_EMC0_SIZE SZ_2K
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#define TEGRA_EMC1_BASE 0x7001A800
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#define TEGRA_EMC1_SIZE SZ_2K
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#define TEGRA124_EMC_BASE 0x7001B000
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#define TEGRA124_EMC_SIZE SZ_2K
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#define TEGRA_CSITE_BASE 0x70040000
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#define TEGRA_CSITE_SIZE SZ_256K
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/* On TEGRA, many peripherals are very closely packed in
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* two 256MB io windows (that actually only use about 64KB
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* at the start of each).
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*
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* We will just map the first MMU section of each window (to minimize
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* pt entries needed) and provide a macro to transform physical
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* io addresses to an appropriate void __iomem *.
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*/
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#define IO_IRAM_PHYS 0x40000000
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#define IO_IRAM_VIRT IOMEM(0xFE400000)
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#define IO_IRAM_SIZE SZ_256K
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#define IO_CPU_PHYS 0x50040000
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#define IO_CPU_VIRT IOMEM(0xFE440000)
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#define IO_CPU_SIZE SZ_16K
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#define IO_PPSB_PHYS 0x60000000
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#define IO_PPSB_VIRT IOMEM(0xFE200000)
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#define IO_PPSB_SIZE SECTION_SIZE
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#define IO_APB_PHYS 0x70000000
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#define IO_APB_VIRT IOMEM(0xFE000000)
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#define IO_APB_SIZE SECTION_SIZE
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#define IO_TO_VIRT_BETWEEN(p, st, sz) ((p) >= (st) && (p) < ((st) + (sz)))
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#define IO_TO_VIRT_XLATE(p, pst, vst) (((p) - (pst) + (vst)))
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#define IO_TO_VIRT(n) ( \
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IO_TO_VIRT_BETWEEN((n), IO_PPSB_PHYS, IO_PPSB_SIZE) ? \
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IO_TO_VIRT_XLATE((n), IO_PPSB_PHYS, IO_PPSB_VIRT) : \
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IO_TO_VIRT_BETWEEN((n), IO_APB_PHYS, IO_APB_SIZE) ? \
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IO_TO_VIRT_XLATE((n), IO_APB_PHYS, IO_APB_VIRT) : \
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IO_TO_VIRT_BETWEEN((n), IO_CPU_PHYS, IO_CPU_SIZE) ? \
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IO_TO_VIRT_XLATE((n), IO_CPU_PHYS, IO_CPU_VIRT) : \
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IO_TO_VIRT_BETWEEN((n), IO_IRAM_PHYS, IO_IRAM_SIZE) ? \
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IO_TO_VIRT_XLATE((n), IO_IRAM_PHYS, IO_IRAM_VIRT) : \
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NULL)
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#define IO_ADDRESS(n) (IO_TO_VIRT(n))
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#endif
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