forked from mirrors/linux
2725f3778f
When CONFIG_MIPS_FP_SUPPORT=n we don't support floating point & so don't need to preserve floating point context for tasks. Remove that context from struct task_struct. Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/21013/ Cc: linux-mips@linux-mips.org
443 lines
12 KiB
C
443 lines
12 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1994 Waldorf GMBH
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* Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
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* Copyright (C) 1996 Paul M. Antoine
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* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
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*/
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#ifndef _ASM_PROCESSOR_H
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#define _ASM_PROCESSOR_H
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#include <linux/atomic.h>
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#include <linux/cpumask.h>
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#include <linux/sizes.h>
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#include <linux/threads.h>
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#include <asm/cachectl.h>
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#include <asm/cpu.h>
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#include <asm/cpu-info.h>
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#include <asm/dsemul.h>
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#include <asm/mipsregs.h>
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#include <asm/prefetch.h>
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/*
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* System setup and hardware flags..
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*/
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extern unsigned int vced_count, vcei_count;
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/*
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* MIPS does have an arch_pick_mmap_layout()
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*/
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#define HAVE_ARCH_PICK_MMAP_LAYOUT 1
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#ifdef CONFIG_32BIT
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#ifdef CONFIG_KVM_GUEST
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/* User space process size is limited to 1GB in KVM Guest Mode */
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#define TASK_SIZE 0x3fff8000UL
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#else
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/*
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* User space process size: 2GB. This is hardcoded into a few places,
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* so don't change it unless you know what you are doing.
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*/
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#define TASK_SIZE 0x80000000UL
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#endif
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#define STACK_TOP_MAX TASK_SIZE
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#define TASK_IS_32BIT_ADDR 1
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#endif
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#ifdef CONFIG_64BIT
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/*
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* User space process size: 1TB. This is hardcoded into a few places,
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* so don't change it unless you know what you are doing. TASK_SIZE
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* is limited to 1TB by the R4000 architecture; R10000 and better can
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* support 16TB; the architectural reserve for future expansion is
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* 8192EB ...
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*/
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#define TASK_SIZE32 0x7fff8000UL
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#ifdef CONFIG_MIPS_VA_BITS_48
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#define TASK_SIZE64 (0x1UL << ((cpu_data[0].vmbits>48)?48:cpu_data[0].vmbits))
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#else
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#define TASK_SIZE64 0x10000000000UL
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#endif
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#define TASK_SIZE (test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)
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#define STACK_TOP_MAX TASK_SIZE64
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#define TASK_SIZE_OF(tsk) \
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(test_tsk_thread_flag(tsk, TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)
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#define TASK_IS_32BIT_ADDR test_thread_flag(TIF_32BIT_ADDR)
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#endif
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#define VDSO_RANDOMIZE_SIZE (TASK_IS_32BIT_ADDR ? SZ_1M : SZ_64M)
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extern unsigned long mips_stack_top(void);
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#define STACK_TOP mips_stack_top()
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/*
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* This decides where the kernel will search for a free chunk of vm
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* space during mmap's.
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*/
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#define TASK_UNMAPPED_BASE PAGE_ALIGN(TASK_SIZE / 3)
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#define NUM_FPU_REGS 32
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#ifdef CONFIG_CPU_HAS_MSA
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# define FPU_REG_WIDTH 128
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#else
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# define FPU_REG_WIDTH 64
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#endif
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union fpureg {
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__u32 val32[FPU_REG_WIDTH / 32];
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__u64 val64[FPU_REG_WIDTH / 64];
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};
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#ifdef CONFIG_CPU_LITTLE_ENDIAN
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# define FPR_IDX(width, idx) (idx)
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#else
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# define FPR_IDX(width, idx) ((idx) ^ ((64 / (width)) - 1))
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#endif
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#define BUILD_FPR_ACCESS(width) \
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static inline u##width get_fpr##width(union fpureg *fpr, unsigned idx) \
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{ \
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return fpr->val##width[FPR_IDX(width, idx)]; \
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} \
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\
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static inline void set_fpr##width(union fpureg *fpr, unsigned idx, \
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u##width val) \
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{ \
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fpr->val##width[FPR_IDX(width, idx)] = val; \
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}
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BUILD_FPR_ACCESS(32)
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BUILD_FPR_ACCESS(64)
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/*
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* It would be nice to add some more fields for emulator statistics,
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* the additional information is private to the FPU emulator for now.
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* See arch/mips/include/asm/fpu_emulator.h.
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*/
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struct mips_fpu_struct {
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union fpureg fpr[NUM_FPU_REGS];
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unsigned int fcr31;
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unsigned int msacsr;
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};
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#define NUM_DSP_REGS 6
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typedef unsigned long dspreg_t;
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struct mips_dsp_state {
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dspreg_t dspr[NUM_DSP_REGS];
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unsigned int dspcontrol;
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};
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#define INIT_CPUMASK { \
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{0,} \
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}
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struct mips3264_watch_reg_state {
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/* The width of watchlo is 32 in a 32 bit kernel and 64 in a
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64 bit kernel. We use unsigned long as it has the same
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property. */
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unsigned long watchlo[NUM_WATCH_REGS];
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/* Only the mask and IRW bits from watchhi. */
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u16 watchhi[NUM_WATCH_REGS];
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};
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union mips_watch_reg_state {
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struct mips3264_watch_reg_state mips3264;
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};
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#if defined(CONFIG_CPU_CAVIUM_OCTEON)
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struct octeon_cop2_state {
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/* DMFC2 rt, 0x0201 */
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unsigned long cop2_crc_iv;
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/* DMFC2 rt, 0x0202 (Set with DMTC2 rt, 0x1202) */
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unsigned long cop2_crc_length;
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/* DMFC2 rt, 0x0200 (set with DMTC2 rt, 0x4200) */
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unsigned long cop2_crc_poly;
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/* DMFC2 rt, 0x0402; DMFC2 rt, 0x040A */
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unsigned long cop2_llm_dat[2];
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/* DMFC2 rt, 0x0084 */
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unsigned long cop2_3des_iv;
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/* DMFC2 rt, 0x0080; DMFC2 rt, 0x0081; DMFC2 rt, 0x0082 */
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unsigned long cop2_3des_key[3];
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/* DMFC2 rt, 0x0088 (Set with DMTC2 rt, 0x0098) */
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unsigned long cop2_3des_result;
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/* DMFC2 rt, 0x0111 (FIXME: Read Pass1 Errata) */
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unsigned long cop2_aes_inp0;
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/* DMFC2 rt, 0x0102; DMFC2 rt, 0x0103 */
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unsigned long cop2_aes_iv[2];
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/* DMFC2 rt, 0x0104; DMFC2 rt, 0x0105; DMFC2 rt, 0x0106; DMFC2
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* rt, 0x0107 */
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unsigned long cop2_aes_key[4];
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/* DMFC2 rt, 0x0110 */
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unsigned long cop2_aes_keylen;
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/* DMFC2 rt, 0x0100; DMFC2 rt, 0x0101 */
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unsigned long cop2_aes_result[2];
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/* DMFC2 rt, 0x0240; DMFC2 rt, 0x0241; DMFC2 rt, 0x0242; DMFC2
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* rt, 0x0243; DMFC2 rt, 0x0244; DMFC2 rt, 0x0245; DMFC2 rt,
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* 0x0246; DMFC2 rt, 0x0247; DMFC2 rt, 0x0248; DMFC2 rt,
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* 0x0249; DMFC2 rt, 0x024A; DMFC2 rt, 0x024B; DMFC2 rt,
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* 0x024C; DMFC2 rt, 0x024D; DMFC2 rt, 0x024E - Pass2 */
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unsigned long cop2_hsh_datw[15];
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/* DMFC2 rt, 0x0250; DMFC2 rt, 0x0251; DMFC2 rt, 0x0252; DMFC2
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* rt, 0x0253; DMFC2 rt, 0x0254; DMFC2 rt, 0x0255; DMFC2 rt,
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* 0x0256; DMFC2 rt, 0x0257 - Pass2 */
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unsigned long cop2_hsh_ivw[8];
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/* DMFC2 rt, 0x0258; DMFC2 rt, 0x0259 - Pass2 */
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unsigned long cop2_gfm_mult[2];
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/* DMFC2 rt, 0x025E - Pass2 */
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unsigned long cop2_gfm_poly;
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/* DMFC2 rt, 0x025A; DMFC2 rt, 0x025B - Pass2 */
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unsigned long cop2_gfm_result[2];
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/* DMFC2 rt, 0x24F, DMFC2 rt, 0x50, OCTEON III */
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unsigned long cop2_sha3[2];
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};
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#define COP2_INIT \
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.cp2 = {0,},
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struct octeon_cvmseg_state {
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unsigned long cvmseg[CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE]
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[cpu_dcache_line_size() / sizeof(unsigned long)];
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};
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#elif defined(CONFIG_CPU_XLP)
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struct nlm_cop2_state {
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u64 rx[4];
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u64 tx[4];
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u32 tx_msg_status;
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u32 rx_msg_status;
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};
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#define COP2_INIT \
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.cp2 = {{0}, {0}, 0, 0},
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#else
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#define COP2_INIT
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#endif
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typedef struct {
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unsigned long seg;
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} mm_segment_t;
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#ifdef CONFIG_CPU_HAS_MSA
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# define ARCH_MIN_TASKALIGN 16
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# define FPU_ALIGN __aligned(16)
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#else
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# define ARCH_MIN_TASKALIGN 8
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# define FPU_ALIGN
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#endif
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struct mips_abi;
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/*
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* If you change thread_struct remember to change the #defines below too!
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*/
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struct thread_struct {
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/* Saved main processor registers. */
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unsigned long reg16;
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unsigned long reg17, reg18, reg19, reg20, reg21, reg22, reg23;
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unsigned long reg29, reg30, reg31;
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/* Saved cp0 stuff. */
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unsigned long cp0_status;
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#ifdef CONFIG_MIPS_FP_SUPPORT
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/* Saved fpu/fpu emulator stuff. */
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struct mips_fpu_struct fpu FPU_ALIGN;
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#endif
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/* Assigned branch delay slot 'emulation' frame */
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atomic_t bd_emu_frame;
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/* PC of the branch from a branch delay slot 'emulation' */
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unsigned long bd_emu_branch_pc;
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/* PC to continue from following a branch delay slot 'emulation' */
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unsigned long bd_emu_cont_pc;
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#ifdef CONFIG_MIPS_MT_FPAFF
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/* Emulated instruction count */
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unsigned long emulated_fp;
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/* Saved per-thread scheduler affinity mask */
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cpumask_t user_cpus_allowed;
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#endif /* CONFIG_MIPS_MT_FPAFF */
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/* Saved state of the DSP ASE, if available. */
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struct mips_dsp_state dsp;
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/* Saved watch register state, if available. */
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union mips_watch_reg_state watch;
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/* Other stuff associated with the thread. */
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unsigned long cp0_badvaddr; /* Last user fault */
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unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */
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unsigned long error_code;
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unsigned long trap_nr;
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#ifdef CONFIG_CPU_CAVIUM_OCTEON
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struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128)));
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struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128)));
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#endif
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#ifdef CONFIG_CPU_XLP
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struct nlm_cop2_state cp2;
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#endif
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struct mips_abi *abi;
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};
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#ifdef CONFIG_MIPS_MT_FPAFF
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#define FPAFF_INIT \
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.emulated_fp = 0, \
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.user_cpus_allowed = INIT_CPUMASK,
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#else
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#define FPAFF_INIT
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#endif /* CONFIG_MIPS_MT_FPAFF */
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#ifdef CONFIG_MIPS_FP_SUPPORT
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# define FPU_INIT \
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.fpu = { \
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.fpr = {{{0,},},}, \
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.fcr31 = 0, \
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.msacsr = 0, \
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},
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#else
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# define FPU_INIT
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#endif
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#define INIT_THREAD { \
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/* \
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* Saved main processor registers \
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*/ \
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.reg16 = 0, \
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.reg17 = 0, \
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.reg18 = 0, \
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.reg19 = 0, \
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.reg20 = 0, \
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.reg21 = 0, \
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.reg22 = 0, \
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.reg23 = 0, \
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.reg29 = 0, \
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.reg30 = 0, \
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.reg31 = 0, \
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/* \
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* Saved cp0 stuff \
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*/ \
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.cp0_status = 0, \
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/* \
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* Saved FPU/FPU emulator stuff \
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*/ \
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FPU_INIT \
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/* \
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* FPU affinity state (null if not FPAFF) \
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*/ \
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FPAFF_INIT \
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/* Delay slot emulation */ \
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.bd_emu_frame = ATOMIC_INIT(BD_EMUFRAME_NONE), \
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.bd_emu_branch_pc = 0, \
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.bd_emu_cont_pc = 0, \
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/* \
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* Saved DSP stuff \
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*/ \
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.dsp = { \
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.dspr = {0, }, \
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.dspcontrol = 0, \
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}, \
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/* \
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* saved watch register stuff \
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*/ \
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.watch = {{{0,},},}, \
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/* \
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* Other stuff associated with the process \
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*/ \
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.cp0_badvaddr = 0, \
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.cp0_baduaddr = 0, \
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.error_code = 0, \
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.trap_nr = 0, \
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/* \
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* Platform specific cop2 registers(null if no COP2) \
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*/ \
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COP2_INIT \
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}
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struct task_struct;
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/* Free all resources held by a thread. */
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#define release_thread(thread) do { } while(0)
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/*
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* Do necessary setup to start up a newly executed thread.
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*/
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extern void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp);
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static inline void flush_thread(void)
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{
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}
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unsigned long get_wchan(struct task_struct *p);
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#define __KSTK_TOS(tsk) ((unsigned long)task_stack_page(tsk) + \
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THREAD_SIZE - 32 - sizeof(struct pt_regs))
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#define task_pt_regs(tsk) ((struct pt_regs *)__KSTK_TOS(tsk))
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#define KSTK_EIP(tsk) (task_pt_regs(tsk)->cp0_epc)
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#define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[29])
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#define KSTK_STATUS(tsk) (task_pt_regs(tsk)->cp0_status)
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#ifdef CONFIG_CPU_LOONGSON3
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/*
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* Loongson-3's SFB (Store-Fill-Buffer) may buffer writes indefinitely when a
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* tight read loop is executed, because reads take priority over writes & the
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* hardware (incorrectly) doesn't ensure that writes will eventually occur.
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*
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* Since spin loops of any kind should have a cpu_relax() in them, force an SFB
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* flush from cpu_relax() such that any pending writes will become visible as
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* expected.
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*/
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#define cpu_relax() smp_mb()
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#else
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#define cpu_relax() barrier()
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#endif
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/*
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* Return_address is a replacement for __builtin_return_address(count)
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* which on certain architectures cannot reasonably be implemented in GCC
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* (MIPS, Alpha) or is unusable with -fomit-frame-pointer (i386).
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* Note that __builtin_return_address(x>=1) is forbidden because GCC
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* aborts compilation on some CPUs. It's simply not possible to unwind
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* some CPU's stackframes.
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*
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* __builtin_return_address works only for non-leaf functions. We avoid the
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* overhead of a function call by forcing the compiler to save the return
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* address register on the stack.
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*/
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#define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);})
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#ifdef CONFIG_CPU_HAS_PREFETCH
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#define ARCH_HAS_PREFETCH
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#define prefetch(x) __builtin_prefetch((x), 0, 1)
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#define ARCH_HAS_PREFETCHW
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#define prefetchw(x) __builtin_prefetch((x), 1, 1)
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#endif
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/*
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* Functions & macros implementing the PR_GET_FP_MODE & PR_SET_FP_MODE options
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* to the prctl syscall.
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*/
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extern int mips_get_process_fp_mode(struct task_struct *task);
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extern int mips_set_process_fp_mode(struct task_struct *task,
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unsigned int value);
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#define GET_FP_MODE(task) mips_get_process_fp_mode(task)
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#define SET_FP_MODE(task,value) mips_set_process_fp_mode(task, value)
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#endif /* _ASM_PROCESSOR_H */
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