forked from mirrors/linux
bf72630130
The text_dma.S code uses its own macro to generate an inline version of an expoline. To make it easier to identify all expolines in the kernel use a thunk and a branch to the thunk just like the rest of the kernel code does it. The name of the text_dma.S expoline thunk is __dma__s390_indirect_jump_r14 and the section is named .dma.text.__s390_indirect_jump_r14. This will be needed for the objtool support. Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
184 lines
3.6 KiB
ArmAsm
184 lines
3.6 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Code that needs to run below 2 GB.
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*
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* Copyright IBM Corp. 2019
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*/
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#include <linux/linkage.h>
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#include <asm/errno.h>
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#include <asm/sigp.h>
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#ifdef CC_USING_EXPOLINE
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.pushsection .dma.text.__s390_indirect_jump_r14,"axG"
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__dma__s390_indirect_jump_r14:
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larl %r1,0f
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ex 0,0(%r1)
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j .
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0: br %r14
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.popsection
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#endif
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.section .dma.text,"ax"
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/*
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* Simplified version of expoline thunk. The normal thunks can not be used here,
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* because they might be more than 2 GB away, and not reachable by the relative
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* branch. No comdat, exrl, etc. optimizations used here, because it only
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* affects a few functions that are not performance-relevant.
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*/
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.macro BR_EX_DMA_r14
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#ifdef CC_USING_EXPOLINE
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jg __dma__s390_indirect_jump_r14
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#else
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br %r14
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#endif
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.endm
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/*
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* int _diag14_dma(unsigned long rx, unsigned long ry1, unsigned long subcode)
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*/
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ENTRY(_diag14_dma)
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lgr %r1,%r2
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lgr %r2,%r3
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lgr %r3,%r4
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lhi %r5,-EIO
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sam31
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diag %r1,%r2,0x14
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.Ldiag14_ex:
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ipm %r5
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srl %r5,28
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.Ldiag14_fault:
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sam64
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lgfr %r2,%r5
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BR_EX_DMA_r14
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EX_TABLE_DMA(.Ldiag14_ex, .Ldiag14_fault)
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ENDPROC(_diag14_dma)
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/*
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* int _diag210_dma(struct diag210 *addr)
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*/
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ENTRY(_diag210_dma)
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lgr %r1,%r2
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lhi %r2,-1
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sam31
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diag %r1,%r0,0x210
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.Ldiag210_ex:
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ipm %r2
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srl %r2,28
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.Ldiag210_fault:
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sam64
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lgfr %r2,%r2
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BR_EX_DMA_r14
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EX_TABLE_DMA(.Ldiag210_ex, .Ldiag210_fault)
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ENDPROC(_diag210_dma)
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/*
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* int _diag26c_dma(void *req, void *resp, enum diag26c_sc subcode)
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*/
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ENTRY(_diag26c_dma)
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lghi %r5,-EOPNOTSUPP
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sam31
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diag %r2,%r4,0x26c
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.Ldiag26c_ex:
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sam64
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lgfr %r2,%r5
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BR_EX_DMA_r14
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EX_TABLE_DMA(.Ldiag26c_ex, .Ldiag26c_ex)
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ENDPROC(_diag26c_dma)
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/*
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* void _diag0c_dma(struct hypfs_diag0c_entry *entry)
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*/
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ENTRY(_diag0c_dma)
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sam31
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diag %r2,%r2,0x0c
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sam64
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BR_EX_DMA_r14
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ENDPROC(_diag0c_dma)
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/*
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* void _swsusp_reset_dma(void)
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*/
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ENTRY(_swsusp_reset_dma)
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larl %r1,restart_entry
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larl %r2,.Lrestart_diag308_psw
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og %r1,0(%r2)
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stg %r1,0(%r0)
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lghi %r0,0
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diag %r0,%r0,0x308
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restart_entry:
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lhi %r1,1
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sigp %r1,%r0,SIGP_SET_ARCHITECTURE
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sam64
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BR_EX_DMA_r14
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ENDPROC(_swsusp_reset_dma)
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/*
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* void _diag308_reset_dma(void)
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*
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* Calls diag 308 subcode 1 and continues execution
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*/
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ENTRY(_diag308_reset_dma)
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larl %r4,.Lctlregs # Save control registers
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stctg %c0,%c15,0(%r4)
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lg %r2,0(%r4) # Disable lowcore protection
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nilh %r2,0xefff
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larl %r4,.Lctlreg0
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stg %r2,0(%r4)
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lctlg %c0,%c0,0(%r4)
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larl %r4,.Lfpctl # Floating point control register
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stfpc 0(%r4)
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larl %r4,.Lprefix # Save prefix register
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stpx 0(%r4)
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larl %r4,.Lprefix_zero # Set prefix register to 0
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spx 0(%r4)
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larl %r4,.Lcontinue_psw # Save PSW flags
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epsw %r2,%r3
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stm %r2,%r3,0(%r4)
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larl %r4,restart_part2 # Setup restart PSW at absolute 0
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larl %r3,.Lrestart_diag308_psw
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og %r4,0(%r3) # Save PSW
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lghi %r3,0
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sturg %r4,%r3 # Use sturg, because of large pages
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lghi %r1,1
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lghi %r0,0
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diag %r0,%r1,0x308
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restart_part2:
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lhi %r0,0 # Load r0 with zero
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lhi %r1,2 # Use mode 2 = ESAME (dump)
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sigp %r1,%r0,SIGP_SET_ARCHITECTURE # Switch to ESAME mode
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sam64 # Switch to 64 bit addressing mode
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larl %r4,.Lctlregs # Restore control registers
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lctlg %c0,%c15,0(%r4)
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larl %r4,.Lfpctl # Restore floating point ctl register
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lfpc 0(%r4)
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larl %r4,.Lprefix # Restore prefix register
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spx 0(%r4)
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larl %r4,.Lcontinue_psw # Restore PSW flags
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lpswe 0(%r4)
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.Lcontinue:
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BR_EX_DMA_r14
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ENDPROC(_diag308_reset_dma)
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.section .dma.data,"aw",@progbits
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.align 8
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.Lrestart_diag308_psw:
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.long 0x00080000,0x80000000
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.align 8
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.Lcontinue_psw:
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.quad 0,.Lcontinue
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.align 8
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.Lctlreg0:
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.quad 0
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.Lctlregs:
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.rept 16
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.quad 0
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.endr
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.Lfpctl:
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.long 0
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.Lprefix:
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.long 0
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.Lprefix_zero:
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.long 0
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