forked from mirrors/linux
457c899653
Add SPDX license identifiers to all files which: - Have no license information of any form - Have EXPORT_.*_SYMBOL_GPL inside which was used in the initial scan/conversion to ignore the file These files fall under the project license, GPL v2 only. The resulting SPDX license identifier is: GPL-2.0-only Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
738 lines
17 KiB
C
738 lines
17 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Low-Level PCI Support for PC
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*
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* (c) 1999--2000 Martin Mares <mj@ucw.cz>
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*/
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#include <linux/sched.h>
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#include <linux/pci.h>
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#include <linux/pci-acpi.h>
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#include <linux/ioport.h>
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#include <linux/init.h>
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#include <linux/dmi.h>
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#include <linux/slab.h>
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#include <asm/acpi.h>
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#include <asm/segment.h>
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#include <asm/io.h>
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#include <asm/smp.h>
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#include <asm/pci_x86.h>
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#include <asm/setup.h>
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unsigned int pci_probe = PCI_PROBE_BIOS | PCI_PROBE_CONF1 | PCI_PROBE_CONF2 |
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PCI_PROBE_MMCONF;
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static int pci_bf_sort;
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int pci_routeirq;
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int noioapicquirk;
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#ifdef CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS
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int noioapicreroute = 0;
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#else
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int noioapicreroute = 1;
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#endif
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int pcibios_last_bus = -1;
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unsigned long pirq_table_addr;
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const struct pci_raw_ops *__read_mostly raw_pci_ops;
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const struct pci_raw_ops *__read_mostly raw_pci_ext_ops;
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int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
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int reg, int len, u32 *val)
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{
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if (domain == 0 && reg < 256 && raw_pci_ops)
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return raw_pci_ops->read(domain, bus, devfn, reg, len, val);
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if (raw_pci_ext_ops)
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return raw_pci_ext_ops->read(domain, bus, devfn, reg, len, val);
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return -EINVAL;
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}
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int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
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int reg, int len, u32 val)
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{
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if (domain == 0 && reg < 256 && raw_pci_ops)
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return raw_pci_ops->write(domain, bus, devfn, reg, len, val);
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if (raw_pci_ext_ops)
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return raw_pci_ext_ops->write(domain, bus, devfn, reg, len, val);
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return -EINVAL;
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}
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static int pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
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{
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return raw_pci_read(pci_domain_nr(bus), bus->number,
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devfn, where, size, value);
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}
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static int pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
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{
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return raw_pci_write(pci_domain_nr(bus), bus->number,
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devfn, where, size, value);
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}
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struct pci_ops pci_root_ops = {
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.read = pci_read,
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.write = pci_write,
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};
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/*
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* This interrupt-safe spinlock protects all accesses to PCI configuration
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* space, except for the mmconfig (ECAM) based operations.
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*/
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DEFINE_RAW_SPINLOCK(pci_config_lock);
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static int __init can_skip_ioresource_align(const struct dmi_system_id *d)
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{
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pci_probe |= PCI_CAN_SKIP_ISA_ALIGN;
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printk(KERN_INFO "PCI: %s detected, can skip ISA alignment\n", d->ident);
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return 0;
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}
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static const struct dmi_system_id can_skip_pciprobe_dmi_table[] __initconst = {
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/*
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* Systems where PCI IO resource ISA alignment can be skipped
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* when the ISA enable bit in the bridge control is not set
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*/
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{
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.callback = can_skip_ioresource_align,
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.ident = "IBM System x3800",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
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DMI_MATCH(DMI_PRODUCT_NAME, "x3800"),
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},
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},
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{
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.callback = can_skip_ioresource_align,
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.ident = "IBM System x3850",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
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DMI_MATCH(DMI_PRODUCT_NAME, "x3850"),
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},
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},
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{
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.callback = can_skip_ioresource_align,
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.ident = "IBM System x3950",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
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DMI_MATCH(DMI_PRODUCT_NAME, "x3950"),
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},
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},
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{}
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};
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void __init dmi_check_skip_isa_align(void)
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{
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dmi_check_system(can_skip_pciprobe_dmi_table);
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}
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static void pcibios_fixup_device_resources(struct pci_dev *dev)
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{
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struct resource *rom_r = &dev->resource[PCI_ROM_RESOURCE];
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struct resource *bar_r;
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int bar;
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if (pci_probe & PCI_NOASSIGN_BARS) {
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/*
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* If the BIOS did not assign the BAR, zero out the
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* resource so the kernel doesn't attempt to assign
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* it later on in pci_assign_unassigned_resources
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*/
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for (bar = 0; bar <= PCI_STD_RESOURCE_END; bar++) {
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bar_r = &dev->resource[bar];
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if (bar_r->start == 0 && bar_r->end != 0) {
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bar_r->flags = 0;
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bar_r->end = 0;
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}
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}
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}
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if (pci_probe & PCI_NOASSIGN_ROMS) {
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if (rom_r->parent)
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return;
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if (rom_r->start) {
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/* we deal with BIOS assigned ROM later */
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return;
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}
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rom_r->start = rom_r->end = rom_r->flags = 0;
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}
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}
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/*
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* Called after each bus is probed, but before its children
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* are examined.
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*/
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void pcibios_fixup_bus(struct pci_bus *b)
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{
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struct pci_dev *dev;
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pci_read_bridge_bases(b);
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list_for_each_entry(dev, &b->devices, bus_list)
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pcibios_fixup_device_resources(dev);
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}
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void pcibios_add_bus(struct pci_bus *bus)
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{
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acpi_pci_add_bus(bus);
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}
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void pcibios_remove_bus(struct pci_bus *bus)
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{
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acpi_pci_remove_bus(bus);
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}
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/*
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* Only use DMI information to set this if nothing was passed
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* on the kernel command line (which was parsed earlier).
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*/
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static int __init set_bf_sort(const struct dmi_system_id *d)
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{
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if (pci_bf_sort == pci_bf_sort_default) {
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pci_bf_sort = pci_dmi_bf;
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printk(KERN_INFO "PCI: %s detected, enabling pci=bfsort.\n", d->ident);
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}
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return 0;
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}
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static void __init read_dmi_type_b1(const struct dmi_header *dm,
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void *private_data)
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{
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u8 *data = (u8 *)dm + 4;
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if (dm->type != 0xB1)
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return;
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if ((((*(u32 *)data) >> 9) & 0x03) == 0x01)
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set_bf_sort((const struct dmi_system_id *)private_data);
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}
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static int __init find_sort_method(const struct dmi_system_id *d)
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{
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dmi_walk(read_dmi_type_b1, (void *)d);
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return 0;
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}
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/*
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* Enable renumbering of PCI bus# ranges to reach all PCI busses (Cardbus)
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*/
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#ifdef __i386__
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static int __init assign_all_busses(const struct dmi_system_id *d)
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{
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pci_probe |= PCI_ASSIGN_ALL_BUSSES;
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printk(KERN_INFO "%s detected: enabling PCI bus# renumbering"
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" (pci=assign-busses)\n", d->ident);
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return 0;
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}
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#endif
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static int __init set_scan_all(const struct dmi_system_id *d)
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{
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printk(KERN_INFO "PCI: %s detected, enabling pci=pcie_scan_all\n",
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d->ident);
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pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
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return 0;
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}
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static const struct dmi_system_id pciprobe_dmi_table[] __initconst = {
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#ifdef __i386__
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/*
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* Laptops which need pci=assign-busses to see Cardbus cards
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*/
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{
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.callback = assign_all_busses,
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.ident = "Samsung X20 Laptop",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "Samsung Electronics"),
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DMI_MATCH(DMI_PRODUCT_NAME, "SX20S"),
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},
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},
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#endif /* __i386__ */
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{
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.callback = set_bf_sort,
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.ident = "Dell PowerEdge 1950",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
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DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge 1950"),
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},
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},
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{
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.callback = set_bf_sort,
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.ident = "Dell PowerEdge 1955",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
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DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge 1955"),
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},
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},
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{
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.callback = set_bf_sort,
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.ident = "Dell PowerEdge 2900",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
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DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge 2900"),
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},
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},
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{
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.callback = set_bf_sort,
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.ident = "Dell PowerEdge 2950",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
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DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge 2950"),
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},
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},
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{
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.callback = set_bf_sort,
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.ident = "Dell PowerEdge R900",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
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DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge R900"),
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},
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},
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{
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.callback = find_sort_method,
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.ident = "Dell System",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc"),
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},
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},
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{
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.callback = set_bf_sort,
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.ident = "HP ProLiant BL20p G3",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "HP"),
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DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL20p G3"),
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},
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},
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{
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.callback = set_bf_sort,
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.ident = "HP ProLiant BL20p G4",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "HP"),
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DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL20p G4"),
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},
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},
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{
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.callback = set_bf_sort,
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.ident = "HP ProLiant BL30p G1",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "HP"),
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DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL30p G1"),
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},
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},
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{
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.callback = set_bf_sort,
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.ident = "HP ProLiant BL25p G1",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "HP"),
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DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL25p G1"),
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},
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},
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{
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.callback = set_bf_sort,
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.ident = "HP ProLiant BL35p G1",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "HP"),
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DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL35p G1"),
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},
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},
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{
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.callback = set_bf_sort,
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.ident = "HP ProLiant BL45p G1",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "HP"),
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DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL45p G1"),
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},
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},
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{
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.callback = set_bf_sort,
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.ident = "HP ProLiant BL45p G2",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "HP"),
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DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL45p G2"),
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},
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},
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{
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.callback = set_bf_sort,
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.ident = "HP ProLiant BL460c G1",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "HP"),
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DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL460c G1"),
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},
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},
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{
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.callback = set_bf_sort,
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.ident = "HP ProLiant BL465c G1",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "HP"),
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DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL465c G1"),
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},
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},
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{
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.callback = set_bf_sort,
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.ident = "HP ProLiant BL480c G1",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "HP"),
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DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL480c G1"),
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},
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},
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{
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.callback = set_bf_sort,
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.ident = "HP ProLiant BL685c G1",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "HP"),
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DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL685c G1"),
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},
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},
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{
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.callback = set_bf_sort,
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.ident = "HP ProLiant DL360",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "HP"),
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DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant DL360"),
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},
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},
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{
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.callback = set_bf_sort,
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.ident = "HP ProLiant DL380",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "HP"),
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DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant DL380"),
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},
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},
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#ifdef __i386__
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{
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.callback = assign_all_busses,
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.ident = "Compaq EVO N800c",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "Compaq"),
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DMI_MATCH(DMI_PRODUCT_NAME, "EVO N800c"),
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},
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},
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#endif
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{
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.callback = set_bf_sort,
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.ident = "HP ProLiant DL385 G2",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "HP"),
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DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant DL385 G2"),
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},
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},
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{
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.callback = set_bf_sort,
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.ident = "HP ProLiant DL585 G2",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "HP"),
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DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant DL585 G2"),
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},
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},
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{
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.callback = set_scan_all,
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.ident = "Stratus/NEC ftServer",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "Stratus"),
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DMI_MATCH(DMI_PRODUCT_NAME, "ftServer"),
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},
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},
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{
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.callback = set_scan_all,
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.ident = "Stratus/NEC ftServer",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "NEC"),
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DMI_MATCH(DMI_PRODUCT_NAME, "Express5800/R32"),
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},
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},
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{
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.callback = set_scan_all,
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.ident = "Stratus/NEC ftServer",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "NEC"),
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DMI_MATCH(DMI_PRODUCT_NAME, "Express5800/R31"),
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},
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},
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{}
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};
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void __init dmi_check_pciprobe(void)
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{
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dmi_check_system(pciprobe_dmi_table);
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}
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void pcibios_scan_root(int busnum)
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{
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struct pci_bus *bus;
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struct pci_sysdata *sd;
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LIST_HEAD(resources);
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sd = kzalloc(sizeof(*sd), GFP_KERNEL);
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if (!sd) {
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printk(KERN_ERR "PCI: OOM, skipping PCI bus %02x\n", busnum);
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return;
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}
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sd->node = x86_pci_root_bus_node(busnum);
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x86_pci_root_bus_resources(busnum, &resources);
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printk(KERN_DEBUG "PCI: Probing PCI hardware (bus %02x)\n", busnum);
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bus = pci_scan_root_bus(NULL, busnum, &pci_root_ops, sd, &resources);
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if (!bus) {
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pci_free_resource_list(&resources);
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kfree(sd);
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return;
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}
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pci_bus_add_devices(bus);
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}
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void __init pcibios_set_cache_line_size(void)
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{
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struct cpuinfo_x86 *c = &boot_cpu_data;
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|
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/*
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* Set PCI cacheline size to that of the CPU if the CPU has reported it.
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* (For older CPUs that don't support cpuid, we se it to 32 bytes
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* It's also good for 386/486s (which actually have 16)
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* as quite a few PCI devices do not support smaller values.
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*/
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if (c->x86_clflush_size > 0) {
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pci_dfl_cache_line_size = c->x86_clflush_size >> 2;
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printk(KERN_DEBUG "PCI: pci_cache_line_size set to %d bytes\n",
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pci_dfl_cache_line_size << 2);
|
|
} else {
|
|
pci_dfl_cache_line_size = 32 >> 2;
|
|
printk(KERN_DEBUG "PCI: Unknown cacheline size. Setting to 32 bytes\n");
|
|
}
|
|
}
|
|
|
|
int __init pcibios_init(void)
|
|
{
|
|
if (!raw_pci_ops && !raw_pci_ext_ops) {
|
|
printk(KERN_WARNING "PCI: System does not support PCI\n");
|
|
return 0;
|
|
}
|
|
|
|
pcibios_set_cache_line_size();
|
|
pcibios_resource_survey();
|
|
|
|
if (pci_bf_sort >= pci_force_bf)
|
|
pci_sort_breadthfirst();
|
|
return 0;
|
|
}
|
|
|
|
char *__init pcibios_setup(char *str)
|
|
{
|
|
if (!strcmp(str, "off")) {
|
|
pci_probe = 0;
|
|
return NULL;
|
|
} else if (!strcmp(str, "bfsort")) {
|
|
pci_bf_sort = pci_force_bf;
|
|
return NULL;
|
|
} else if (!strcmp(str, "nobfsort")) {
|
|
pci_bf_sort = pci_force_nobf;
|
|
return NULL;
|
|
}
|
|
#ifdef CONFIG_PCI_BIOS
|
|
else if (!strcmp(str, "bios")) {
|
|
pci_probe = PCI_PROBE_BIOS;
|
|
return NULL;
|
|
} else if (!strcmp(str, "nobios")) {
|
|
pci_probe &= ~PCI_PROBE_BIOS;
|
|
return NULL;
|
|
} else if (!strcmp(str, "biosirq")) {
|
|
pci_probe |= PCI_BIOS_IRQ_SCAN;
|
|
return NULL;
|
|
} else if (!strncmp(str, "pirqaddr=", 9)) {
|
|
pirq_table_addr = simple_strtoul(str+9, NULL, 0);
|
|
return NULL;
|
|
}
|
|
#endif
|
|
#ifdef CONFIG_PCI_DIRECT
|
|
else if (!strcmp(str, "conf1")) {
|
|
pci_probe = PCI_PROBE_CONF1 | PCI_NO_CHECKS;
|
|
return NULL;
|
|
}
|
|
else if (!strcmp(str, "conf2")) {
|
|
pci_probe = PCI_PROBE_CONF2 | PCI_NO_CHECKS;
|
|
return NULL;
|
|
}
|
|
#endif
|
|
#ifdef CONFIG_PCI_MMCONFIG
|
|
else if (!strcmp(str, "nommconf")) {
|
|
pci_probe &= ~PCI_PROBE_MMCONF;
|
|
return NULL;
|
|
}
|
|
else if (!strcmp(str, "check_enable_amd_mmconf")) {
|
|
pci_probe |= PCI_CHECK_ENABLE_AMD_MMCONF;
|
|
return NULL;
|
|
}
|
|
#endif
|
|
else if (!strcmp(str, "noacpi")) {
|
|
acpi_noirq_set();
|
|
return NULL;
|
|
}
|
|
else if (!strcmp(str, "noearly")) {
|
|
pci_probe |= PCI_PROBE_NOEARLY;
|
|
return NULL;
|
|
}
|
|
else if (!strcmp(str, "usepirqmask")) {
|
|
pci_probe |= PCI_USE_PIRQ_MASK;
|
|
return NULL;
|
|
} else if (!strncmp(str, "irqmask=", 8)) {
|
|
pcibios_irq_mask = simple_strtol(str+8, NULL, 0);
|
|
return NULL;
|
|
} else if (!strncmp(str, "lastbus=", 8)) {
|
|
pcibios_last_bus = simple_strtol(str+8, NULL, 0);
|
|
return NULL;
|
|
} else if (!strcmp(str, "rom")) {
|
|
pci_probe |= PCI_ASSIGN_ROMS;
|
|
return NULL;
|
|
} else if (!strcmp(str, "norom")) {
|
|
pci_probe |= PCI_NOASSIGN_ROMS;
|
|
return NULL;
|
|
} else if (!strcmp(str, "nobar")) {
|
|
pci_probe |= PCI_NOASSIGN_BARS;
|
|
return NULL;
|
|
} else if (!strcmp(str, "assign-busses")) {
|
|
pci_probe |= PCI_ASSIGN_ALL_BUSSES;
|
|
return NULL;
|
|
} else if (!strcmp(str, "use_crs")) {
|
|
pci_probe |= PCI_USE__CRS;
|
|
return NULL;
|
|
} else if (!strcmp(str, "nocrs")) {
|
|
pci_probe |= PCI_ROOT_NO_CRS;
|
|
return NULL;
|
|
#ifdef CONFIG_PHYS_ADDR_T_64BIT
|
|
} else if (!strcmp(str, "big_root_window")) {
|
|
pci_probe |= PCI_BIG_ROOT_WINDOW;
|
|
return NULL;
|
|
#endif
|
|
} else if (!strcmp(str, "routeirq")) {
|
|
pci_routeirq = 1;
|
|
return NULL;
|
|
} else if (!strcmp(str, "skip_isa_align")) {
|
|
pci_probe |= PCI_CAN_SKIP_ISA_ALIGN;
|
|
return NULL;
|
|
} else if (!strcmp(str, "noioapicquirk")) {
|
|
noioapicquirk = 1;
|
|
return NULL;
|
|
} else if (!strcmp(str, "ioapicreroute")) {
|
|
if (noioapicreroute != -1)
|
|
noioapicreroute = 0;
|
|
return NULL;
|
|
} else if (!strcmp(str, "noioapicreroute")) {
|
|
if (noioapicreroute != -1)
|
|
noioapicreroute = 1;
|
|
return NULL;
|
|
}
|
|
return str;
|
|
}
|
|
|
|
unsigned int pcibios_assign_all_busses(void)
|
|
{
|
|
return (pci_probe & PCI_ASSIGN_ALL_BUSSES) ? 1 : 0;
|
|
}
|
|
|
|
#if defined(CONFIG_X86_DEV_DMA_OPS) && defined(CONFIG_PCI_DOMAINS)
|
|
static LIST_HEAD(dma_domain_list);
|
|
static DEFINE_SPINLOCK(dma_domain_list_lock);
|
|
|
|
void add_dma_domain(struct dma_domain *domain)
|
|
{
|
|
spin_lock(&dma_domain_list_lock);
|
|
list_add(&domain->node, &dma_domain_list);
|
|
spin_unlock(&dma_domain_list_lock);
|
|
}
|
|
EXPORT_SYMBOL_GPL(add_dma_domain);
|
|
|
|
void del_dma_domain(struct dma_domain *domain)
|
|
{
|
|
spin_lock(&dma_domain_list_lock);
|
|
list_del(&domain->node);
|
|
spin_unlock(&dma_domain_list_lock);
|
|
}
|
|
EXPORT_SYMBOL_GPL(del_dma_domain);
|
|
|
|
static void set_dma_domain_ops(struct pci_dev *pdev)
|
|
{
|
|
struct dma_domain *domain;
|
|
|
|
spin_lock(&dma_domain_list_lock);
|
|
list_for_each_entry(domain, &dma_domain_list, node) {
|
|
if (pci_domain_nr(pdev->bus) == domain->domain_nr) {
|
|
pdev->dev.dma_ops = domain->dma_ops;
|
|
break;
|
|
}
|
|
}
|
|
spin_unlock(&dma_domain_list_lock);
|
|
}
|
|
#else
|
|
static void set_dma_domain_ops(struct pci_dev *pdev) {}
|
|
#endif
|
|
|
|
static void set_dev_domain_options(struct pci_dev *pdev)
|
|
{
|
|
if (is_vmd(pdev->bus))
|
|
pdev->hotplug_user_indicators = 1;
|
|
}
|
|
|
|
int pcibios_add_device(struct pci_dev *dev)
|
|
{
|
|
struct setup_data *data;
|
|
struct pci_setup_rom *rom;
|
|
u64 pa_data;
|
|
|
|
pa_data = boot_params.hdr.setup_data;
|
|
while (pa_data) {
|
|
data = memremap(pa_data, sizeof(*rom), MEMREMAP_WB);
|
|
if (!data)
|
|
return -ENOMEM;
|
|
|
|
if (data->type == SETUP_PCI) {
|
|
rom = (struct pci_setup_rom *)data;
|
|
|
|
if ((pci_domain_nr(dev->bus) == rom->segment) &&
|
|
(dev->bus->number == rom->bus) &&
|
|
(PCI_SLOT(dev->devfn) == rom->device) &&
|
|
(PCI_FUNC(dev->devfn) == rom->function) &&
|
|
(dev->vendor == rom->vendor) &&
|
|
(dev->device == rom->devid)) {
|
|
dev->rom = pa_data +
|
|
offsetof(struct pci_setup_rom, romdata);
|
|
dev->romlen = rom->pcilen;
|
|
}
|
|
}
|
|
pa_data = data->next;
|
|
memunmap(data);
|
|
}
|
|
set_dma_domain_ops(dev);
|
|
set_dev_domain_options(dev);
|
|
return 0;
|
|
}
|
|
|
|
int pcibios_enable_device(struct pci_dev *dev, int mask)
|
|
{
|
|
int err;
|
|
|
|
if ((err = pci_enable_resources(dev, mask)) < 0)
|
|
return err;
|
|
|
|
if (!pci_dev_msi_enabled(dev))
|
|
return pcibios_enable_irq(dev);
|
|
return 0;
|
|
}
|
|
|
|
void pcibios_disable_device (struct pci_dev *dev)
|
|
{
|
|
if (!pci_dev_msi_enabled(dev) && pcibios_disable_irq)
|
|
pcibios_disable_irq(dev);
|
|
}
|
|
|
|
#ifdef CONFIG_ACPI_HOTPLUG_IOAPIC
|
|
void pcibios_release_device(struct pci_dev *dev)
|
|
{
|
|
if (atomic_dec_return(&dev->enable_cnt) >= 0)
|
|
pcibios_disable_device(dev);
|
|
|
|
}
|
|
#endif
|
|
|
|
int pci_ext_cfg_avail(void)
|
|
{
|
|
if (raw_pci_ext_ops)
|
|
return 1;
|
|
else
|
|
return 0;
|
|
}
|