forked from mirrors/linux
2e62246b08
ROHM bd71837 andbd71847contain 32768Hz clock gate. Support the clock using generic clock framework. Note, only bd71837 is tested butbd71847should be identical what comes to clk parts. Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
123 lines
2.8 KiB
C
123 lines
2.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (C) 2018 ROHM Semiconductors
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/err.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/mfd/rohm-bd718x7.h>
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/regmap.h>
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struct bd718xx_clk {
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struct clk_hw hw;
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u8 reg;
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u8 mask;
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struct platform_device *pdev;
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struct bd718xx *mfd;
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};
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static int bd71837_clk_set(struct clk_hw *hw, int status)
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{
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struct bd718xx_clk *c = container_of(hw, struct bd718xx_clk, hw);
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return regmap_update_bits(c->mfd->regmap, c->reg, c->mask, status);
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}
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static void bd71837_clk_disable(struct clk_hw *hw)
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{
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int rv;
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struct bd718xx_clk *c = container_of(hw, struct bd718xx_clk, hw);
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rv = bd71837_clk_set(hw, 0);
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if (rv)
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dev_dbg(&c->pdev->dev, "Failed to disable 32K clk (%d)\n", rv);
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}
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static int bd71837_clk_enable(struct clk_hw *hw)
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{
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return bd71837_clk_set(hw, 1);
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}
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static int bd71837_clk_is_enabled(struct clk_hw *hw)
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{
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int enabled;
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int rval;
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struct bd718xx_clk *c = container_of(hw, struct bd718xx_clk, hw);
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rval = regmap_read(c->mfd->regmap, c->reg, &enabled);
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if (rval)
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return rval;
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return enabled & c->mask;
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}
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static const struct clk_ops bd71837_clk_ops = {
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.prepare = &bd71837_clk_enable,
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.unprepare = &bd71837_clk_disable,
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.is_prepared = &bd71837_clk_is_enabled,
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};
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static int bd71837_clk_probe(struct platform_device *pdev)
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{
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struct bd718xx_clk *c;
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int rval = -ENOMEM;
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const char *parent_clk;
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struct device *parent = pdev->dev.parent;
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struct bd718xx *mfd = dev_get_drvdata(parent);
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struct clk_init_data init = {
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.name = "bd718xx-32k-out",
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.ops = &bd71837_clk_ops,
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};
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c = devm_kzalloc(&pdev->dev, sizeof(*c), GFP_KERNEL);
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if (!c)
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return -ENOMEM;
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init.num_parents = 1;
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parent_clk = of_clk_get_parent_name(parent->of_node, 0);
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init.parent_names = &parent_clk;
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if (!parent_clk) {
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dev_err(&pdev->dev, "No parent clk found\n");
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return -EINVAL;
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}
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c->reg = BD718XX_REG_OUT32K;
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c->mask = BD718XX_OUT32K_EN;
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c->mfd = mfd;
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c->pdev = pdev;
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c->hw.init = &init;
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of_property_read_string_index(parent->of_node,
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"clock-output-names", 0, &init.name);
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rval = devm_clk_hw_register(&pdev->dev, &c->hw);
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if (rval) {
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dev_err(&pdev->dev, "failed to register 32K clk");
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return rval;
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}
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rval = devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_simple_get,
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&c->hw);
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if (rval)
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dev_err(&pdev->dev, "adding clk provider failed\n");
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return rval;
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}
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static struct platform_driver bd71837_clk = {
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.driver = {
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.name = "bd718xx-clk",
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},
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.probe = bd71837_clk_probe,
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};
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module_platform_driver(bd71837_clk);
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MODULE_AUTHOR("Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>");
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MODULE_DESCRIPTION("BD71837 chip clk driver");
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MODULE_LICENSE("GPL");
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