forked from mirrors/linux
39b8500283
The Meson G12A PCIE PLL is fined tuned to deliver a very precise 100MHz reference clock for the PCIe Analog PHY, and thus requires a strict register sequence to enable the PLL. To simplify, use the _init() op to enable the PLL and keep the other ops except set_rate since the rate is fixed. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lkml.kernel.org/r/20190307141455.23879-2-narmstrong@baylibre.com
50 lines
993 B
C
50 lines
993 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 BayLibre, SAS.
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* Author: Jerome Brunet <jbrunet@baylibre.com>
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*/
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#ifndef __MESON_CLK_PLL_H
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#define __MESON_CLK_PLL_H
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#include <linux/clk-provider.h>
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#include <linux/regmap.h>
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#include "parm.h"
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struct pll_params_table {
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unsigned int m;
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unsigned int n;
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};
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struct pll_mult_range {
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unsigned int min;
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unsigned int max;
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};
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#define PLL_PARAMS(_m, _n) \
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{ \
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.m = (_m), \
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.n = (_n), \
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}
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#define CLK_MESON_PLL_ROUND_CLOSEST BIT(0)
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struct meson_clk_pll_data {
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struct parm en;
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struct parm m;
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struct parm n;
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struct parm frac;
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struct parm l;
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struct parm rst;
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const struct reg_sequence *init_regs;
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unsigned int init_count;
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const struct pll_params_table *table;
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const struct pll_mult_range *range;
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u8 flags;
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};
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extern const struct clk_ops meson_clk_pll_ro_ops;
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extern const struct clk_ops meson_clk_pll_ops;
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extern const struct clk_ops meson_clk_pcie_pll_ops;
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#endif /* __MESON_CLK_PLL_H */
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