forked from mirrors/linux
03963caeb0
This sacrificial copyright header update is offered to the legal department as atonement for any changes made in this driver files in the course of the current year which have not been duly recorded as such. Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
168 lines
8.8 KiB
C
168 lines
8.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (C) 2012-2019 ARM Limited (or its affiliates). */
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#ifndef __CC_CRYS_KERNEL_H__
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#define __CC_CRYS_KERNEL_H__
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// --------------------------------------
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// BLOCK: DSCRPTR
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// --------------------------------------
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#define CC_DSCRPTR_COMPLETION_COUNTER_REG_OFFSET 0xE00UL
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#define CC_DSCRPTR_COMPLETION_COUNTER_COMPLETION_COUNTER_BIT_SHIFT 0x0UL
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#define CC_DSCRPTR_COMPLETION_COUNTER_COMPLETION_COUNTER_BIT_SIZE 0x6UL
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#define CC_DSCRPTR_COMPLETION_COUNTER_OVERFLOW_COUNTER_BIT_SHIFT 0x6UL
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#define CC_DSCRPTR_COMPLETION_COUNTER_OVERFLOW_COUNTER_BIT_SIZE 0x1UL
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#define CC_DSCRPTR_SW_RESET_REG_OFFSET 0xE40UL
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#define CC_DSCRPTR_SW_RESET_VALUE_BIT_SHIFT 0x0UL
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#define CC_DSCRPTR_SW_RESET_VALUE_BIT_SIZE 0x1UL
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#define CC_DSCRPTR_QUEUE_SRAM_SIZE_REG_OFFSET 0xE60UL
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#define CC_DSCRPTR_QUEUE_SRAM_SIZE_NUM_OF_DSCRPTR_BIT_SHIFT 0x0UL
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#define CC_DSCRPTR_QUEUE_SRAM_SIZE_NUM_OF_DSCRPTR_BIT_SIZE 0xAUL
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#define CC_DSCRPTR_QUEUE_SRAM_SIZE_DSCRPTR_SRAM_SIZE_BIT_SHIFT 0xAUL
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#define CC_DSCRPTR_QUEUE_SRAM_SIZE_DSCRPTR_SRAM_SIZE_BIT_SIZE 0xCUL
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#define CC_DSCRPTR_QUEUE_SRAM_SIZE_SRAM_SIZE_BIT_SHIFT 0x16UL
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#define CC_DSCRPTR_QUEUE_SRAM_SIZE_SRAM_SIZE_BIT_SIZE 0x3UL
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#define CC_DSCRPTR_SINGLE_ADDR_EN_REG_OFFSET 0xE64UL
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#define CC_DSCRPTR_SINGLE_ADDR_EN_VALUE_BIT_SHIFT 0x0UL
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#define CC_DSCRPTR_SINGLE_ADDR_EN_VALUE_BIT_SIZE 0x1UL
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#define CC_DSCRPTR_MEASURE_CNTR_REG_OFFSET 0xE68UL
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#define CC_DSCRPTR_MEASURE_CNTR_VALUE_BIT_SHIFT 0x0UL
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#define CC_DSCRPTR_MEASURE_CNTR_VALUE_BIT_SIZE 0x20UL
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#define CC_DSCRPTR_QUEUE_WORD0_REG_OFFSET 0xE80UL
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#define CC_DSCRPTR_QUEUE_WORD0_VALUE_BIT_SHIFT 0x0UL
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#define CC_DSCRPTR_QUEUE_WORD0_VALUE_BIT_SIZE 0x20UL
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#define CC_DSCRPTR_QUEUE_WORD1_REG_OFFSET 0xE84UL
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#define CC_DSCRPTR_QUEUE_WORD1_DIN_DMA_MODE_BIT_SHIFT 0x0UL
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#define CC_DSCRPTR_QUEUE_WORD1_DIN_DMA_MODE_BIT_SIZE 0x2UL
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#define CC_DSCRPTR_QUEUE_WORD1_DIN_SIZE_BIT_SHIFT 0x2UL
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#define CC_DSCRPTR_QUEUE_WORD1_DIN_SIZE_BIT_SIZE 0x18UL
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#define CC_DSCRPTR_QUEUE_WORD1_NS_BIT_BIT_SHIFT 0x1AUL
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#define CC_DSCRPTR_QUEUE_WORD1_NS_BIT_BIT_SIZE 0x1UL
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#define CC_DSCRPTR_QUEUE_WORD1_DIN_CONST_VALUE_BIT_SHIFT 0x1BUL
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#define CC_DSCRPTR_QUEUE_WORD1_DIN_CONST_VALUE_BIT_SIZE 0x1UL
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#define CC_DSCRPTR_QUEUE_WORD1_NOT_LAST_BIT_SHIFT 0x1CUL
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#define CC_DSCRPTR_QUEUE_WORD1_NOT_LAST_BIT_SIZE 0x1UL
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#define CC_DSCRPTR_QUEUE_WORD1_LOCK_QUEUE_BIT_SHIFT 0x1DUL
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#define CC_DSCRPTR_QUEUE_WORD1_LOCK_QUEUE_BIT_SIZE 0x1UL
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#define CC_DSCRPTR_QUEUE_WORD1_NOT_USED_BIT_SHIFT 0x1EUL
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#define CC_DSCRPTR_QUEUE_WORD1_NOT_USED_BIT_SIZE 0x2UL
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#define CC_DSCRPTR_QUEUE_WORD2_REG_OFFSET 0xE88UL
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#define CC_DSCRPTR_QUEUE_WORD2_VALUE_BIT_SHIFT 0x0UL
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#define CC_DSCRPTR_QUEUE_WORD2_VALUE_BIT_SIZE 0x20UL
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#define CC_DSCRPTR_QUEUE_WORD3_REG_OFFSET 0xE8CUL
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#define CC_DSCRPTR_QUEUE_WORD3_DOUT_DMA_MODE_BIT_SHIFT 0x0UL
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#define CC_DSCRPTR_QUEUE_WORD3_DOUT_DMA_MODE_BIT_SIZE 0x2UL
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#define CC_DSCRPTR_QUEUE_WORD3_DOUT_SIZE_BIT_SHIFT 0x2UL
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#define CC_DSCRPTR_QUEUE_WORD3_DOUT_SIZE_BIT_SIZE 0x18UL
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#define CC_DSCRPTR_QUEUE_WORD3_NS_BIT_BIT_SHIFT 0x1AUL
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#define CC_DSCRPTR_QUEUE_WORD3_NS_BIT_BIT_SIZE 0x1UL
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#define CC_DSCRPTR_QUEUE_WORD3_DOUT_LAST_IND_BIT_SHIFT 0x1BUL
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#define CC_DSCRPTR_QUEUE_WORD3_DOUT_LAST_IND_BIT_SIZE 0x1UL
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#define CC_DSCRPTR_QUEUE_WORD3_HASH_XOR_BIT_BIT_SHIFT 0x1DUL
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#define CC_DSCRPTR_QUEUE_WORD3_HASH_XOR_BIT_BIT_SIZE 0x1UL
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#define CC_DSCRPTR_QUEUE_WORD3_NOT_USED_BIT_SHIFT 0x1EUL
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#define CC_DSCRPTR_QUEUE_WORD3_NOT_USED_BIT_SIZE 0x1UL
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#define CC_DSCRPTR_QUEUE_WORD3_QUEUE_LAST_IND_BIT_SHIFT 0x1FUL
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#define CC_DSCRPTR_QUEUE_WORD3_QUEUE_LAST_IND_BIT_SIZE 0x1UL
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#define CC_DSCRPTR_QUEUE_WORD4_REG_OFFSET 0xE90UL
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#define CC_DSCRPTR_QUEUE_WORD4_DATA_FLOW_MODE_BIT_SHIFT 0x0UL
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#define CC_DSCRPTR_QUEUE_WORD4_DATA_FLOW_MODE_BIT_SIZE 0x6UL
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#define CC_DSCRPTR_QUEUE_WORD4_AES_SEL_N_HASH_BIT_SHIFT 0x6UL
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#define CC_DSCRPTR_QUEUE_WORD4_AES_SEL_N_HASH_BIT_SIZE 0x1UL
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#define CC_DSCRPTR_QUEUE_WORD4_AES_XOR_CRYPTO_KEY_BIT_SHIFT 0x7UL
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#define CC_DSCRPTR_QUEUE_WORD4_AES_XOR_CRYPTO_KEY_BIT_SIZE 0x1UL
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#define CC_DSCRPTR_QUEUE_WORD4_ACK_NEEDED_BIT_SHIFT 0x8UL
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#define CC_DSCRPTR_QUEUE_WORD4_ACK_NEEDED_BIT_SIZE 0x2UL
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#define CC_DSCRPTR_QUEUE_WORD4_CIPHER_MODE_BIT_SHIFT 0xAUL
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#define CC_DSCRPTR_QUEUE_WORD4_CIPHER_MODE_BIT_SIZE 0x4UL
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#define CC_DSCRPTR_QUEUE_WORD4_CMAC_SIZE0_BIT_SHIFT 0xEUL
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#define CC_DSCRPTR_QUEUE_WORD4_CMAC_SIZE0_BIT_SIZE 0x1UL
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#define CC_DSCRPTR_QUEUE_WORD4_CIPHER_DO_BIT_SHIFT 0xFUL
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#define CC_DSCRPTR_QUEUE_WORD4_CIPHER_DO_BIT_SIZE 0x2UL
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#define CC_DSCRPTR_QUEUE_WORD4_CIPHER_CONF0_BIT_SHIFT 0x11UL
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#define CC_DSCRPTR_QUEUE_WORD4_CIPHER_CONF0_BIT_SIZE 0x2UL
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#define CC_DSCRPTR_QUEUE_WORD4_CIPHER_CONF1_BIT_SHIFT 0x13UL
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#define CC_DSCRPTR_QUEUE_WORD4_CIPHER_CONF1_BIT_SIZE 0x1UL
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#define CC_DSCRPTR_QUEUE_WORD4_CIPHER_CONF2_BIT_SHIFT 0x14UL
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#define CC_DSCRPTR_QUEUE_WORD4_CIPHER_CONF2_BIT_SIZE 0x2UL
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#define CC_DSCRPTR_QUEUE_WORD4_KEY_SIZE_BIT_SHIFT 0x16UL
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#define CC_DSCRPTR_QUEUE_WORD4_KEY_SIZE_BIT_SIZE 0x2UL
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#define CC_DSCRPTR_QUEUE_WORD4_SETUP_OPERATION_BIT_SHIFT 0x18UL
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#define CC_DSCRPTR_QUEUE_WORD4_SETUP_OPERATION_BIT_SIZE 0x4UL
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#define CC_DSCRPTR_QUEUE_WORD4_DIN_SRAM_ENDIANNESS_BIT_SHIFT 0x1CUL
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#define CC_DSCRPTR_QUEUE_WORD4_DIN_SRAM_ENDIANNESS_BIT_SIZE 0x1UL
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#define CC_DSCRPTR_QUEUE_WORD4_DOUT_SRAM_ENDIANNESS_BIT_SHIFT 0x1DUL
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#define CC_DSCRPTR_QUEUE_WORD4_DOUT_SRAM_ENDIANNESS_BIT_SIZE 0x1UL
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#define CC_DSCRPTR_QUEUE_WORD4_WORD_SWAP_BIT_SHIFT 0x1EUL
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#define CC_DSCRPTR_QUEUE_WORD4_WORD_SWAP_BIT_SIZE 0x1UL
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#define CC_DSCRPTR_QUEUE_WORD4_BYTES_SWAP_BIT_SHIFT 0x1FUL
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#define CC_DSCRPTR_QUEUE_WORD4_BYTES_SWAP_BIT_SIZE 0x1UL
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#define CC_DSCRPTR_QUEUE_WORD5_REG_OFFSET 0xE94UL
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#define CC_DSCRPTR_QUEUE_WORD5_DIN_ADDR_HIGH_BIT_SHIFT 0x0UL
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#define CC_DSCRPTR_QUEUE_WORD5_DIN_ADDR_HIGH_BIT_SIZE 0x10UL
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#define CC_DSCRPTR_QUEUE_WORD5_DOUT_ADDR_HIGH_BIT_SHIFT 0x10UL
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#define CC_DSCRPTR_QUEUE_WORD5_DOUT_ADDR_HIGH_BIT_SIZE 0x10UL
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#define CC_DSCRPTR_QUEUE_WATERMARK_REG_OFFSET 0xE98UL
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#define CC_DSCRPTR_QUEUE_WATERMARK_VALUE_BIT_SHIFT 0x0UL
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#define CC_DSCRPTR_QUEUE_WATERMARK_VALUE_BIT_SIZE 0xAUL
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#define CC_DSCRPTR_QUEUE_CONTENT_REG_OFFSET 0xE9CUL
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#define CC_DSCRPTR_QUEUE_CONTENT_VALUE_BIT_SHIFT 0x0UL
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#define CC_DSCRPTR_QUEUE_CONTENT_VALUE_BIT_SIZE 0xAUL
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// --------------------------------------
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// BLOCK: AXI_P
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// --------------------------------------
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#define CC_AXIM_MON_INFLIGHT_REG_OFFSET 0xB00UL
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#define CC_AXIM_MON_INFLIGHT_VALUE_BIT_SHIFT 0x0UL
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#define CC_AXIM_MON_INFLIGHT_VALUE_BIT_SIZE 0x8UL
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#define CC_AXIM_MON_INFLIGHTLAST_REG_OFFSET 0xB40UL
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#define CC_AXIM_MON_INFLIGHTLAST_VALUE_BIT_SHIFT 0x0UL
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#define CC_AXIM_MON_INFLIGHTLAST_VALUE_BIT_SIZE 0x8UL
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#define CC_AXIM_MON_COMP_REG_OFFSET 0xB80UL
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#define CC_AXIM_MON_COMP8_REG_OFFSET 0xBA0UL
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#define CC_AXIM_MON_COMP_VALUE_BIT_SHIFT 0x0UL
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#define CC_AXIM_MON_COMP_VALUE_BIT_SIZE 0x10UL
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#define CC_AXIM_MON_ERR_REG_OFFSET 0xBC4UL
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#define CC_AXIM_MON_ERR_BRESP_BIT_SHIFT 0x0UL
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#define CC_AXIM_MON_ERR_BRESP_BIT_SIZE 0x2UL
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#define CC_AXIM_MON_ERR_BID_BIT_SHIFT 0x2UL
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#define CC_AXIM_MON_ERR_BID_BIT_SIZE 0x4UL
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#define CC_AXIM_MON_ERR_RRESP_BIT_SHIFT 0x10UL
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#define CC_AXIM_MON_ERR_RRESP_BIT_SIZE 0x2UL
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#define CC_AXIM_MON_ERR_RID_BIT_SHIFT 0x12UL
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#define CC_AXIM_MON_ERR_RID_BIT_SIZE 0x4UL
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#define CC_AXIM_CFG_REG_OFFSET 0xBE8UL
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#define CC_AXIM_CFG_BRESPMASK_BIT_SHIFT 0x4UL
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#define CC_AXIM_CFG_BRESPMASK_BIT_SIZE 0x1UL
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#define CC_AXIM_CFG_RRESPMASK_BIT_SHIFT 0x5UL
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#define CC_AXIM_CFG_RRESPMASK_BIT_SIZE 0x1UL
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#define CC_AXIM_CFG_INFLTMASK_BIT_SHIFT 0x6UL
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#define CC_AXIM_CFG_INFLTMASK_BIT_SIZE 0x1UL
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#define CC_AXIM_CFG_COMPMASK_BIT_SHIFT 0x7UL
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#define CC_AXIM_CFG_COMPMASK_BIT_SIZE 0x1UL
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#define CC_AXIM_ACE_CONST_REG_OFFSET 0xBECUL
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#define CC_AXIM_ACE_CONST_ARDOMAIN_BIT_SHIFT 0x0UL
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#define CC_AXIM_ACE_CONST_ARDOMAIN_BIT_SIZE 0x2UL
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#define CC_AXIM_ACE_CONST_AWDOMAIN_BIT_SHIFT 0x2UL
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#define CC_AXIM_ACE_CONST_AWDOMAIN_BIT_SIZE 0x2UL
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#define CC_AXIM_ACE_CONST_ARBAR_BIT_SHIFT 0x4UL
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#define CC_AXIM_ACE_CONST_ARBAR_BIT_SIZE 0x2UL
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#define CC_AXIM_ACE_CONST_AWBAR_BIT_SHIFT 0x6UL
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#define CC_AXIM_ACE_CONST_AWBAR_BIT_SIZE 0x2UL
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#define CC_AXIM_ACE_CONST_ARSNOOP_BIT_SHIFT 0x8UL
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#define CC_AXIM_ACE_CONST_ARSNOOP_BIT_SIZE 0x4UL
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#define CC_AXIM_ACE_CONST_AWSNOOP_NOT_ALIGNED_BIT_SHIFT 0xCUL
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#define CC_AXIM_ACE_CONST_AWSNOOP_NOT_ALIGNED_BIT_SIZE 0x3UL
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#define CC_AXIM_ACE_CONST_AWSNOOP_ALIGNED_BIT_SHIFT 0xFUL
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#define CC_AXIM_ACE_CONST_AWSNOOP_ALIGNED_BIT_SIZE 0x3UL
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#define CC_AXIM_ACE_CONST_AWADDR_NOT_MASKED_BIT_SHIFT 0x12UL
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#define CC_AXIM_ACE_CONST_AWADDR_NOT_MASKED_BIT_SIZE 0x7UL
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#define CC_AXIM_ACE_CONST_AWLEN_VAL_BIT_SHIFT 0x19UL
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#define CC_AXIM_ACE_CONST_AWLEN_VAL_BIT_SIZE 0x4UL
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#define CC_AXIM_CACHE_PARAMS_REG_OFFSET 0xBF0UL
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#define CC_AXIM_CACHE_PARAMS_AWCACHE_LAST_BIT_SHIFT 0x0UL
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#define CC_AXIM_CACHE_PARAMS_AWCACHE_LAST_BIT_SIZE 0x4UL
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#define CC_AXIM_CACHE_PARAMS_AWCACHE_BIT_SHIFT 0x4UL
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#define CC_AXIM_CACHE_PARAMS_AWCACHE_BIT_SIZE 0x4UL
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#define CC_AXIM_CACHE_PARAMS_ARCACHE_BIT_SHIFT 0x8UL
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#define CC_AXIM_CACHE_PARAMS_ARCACHE_BIT_SIZE 0x4UL
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#endif // __CC_CRYS_KERNEL_H__
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