forked from mirrors/linux
6884db3c5f
Replace the old license information with the corresponding SPDX license. Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
367 lines
9.7 KiB
C
367 lines
9.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* cobalt driver internal defines and structures
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*
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* Derived from cx18-driver.h
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*
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* Copyright 2012-2015 Cisco Systems, Inc. and/or its affiliates.
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* All rights reserved.
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*/
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#ifndef COBALT_DRIVER_H
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#define COBALT_DRIVER_H
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/spinlock.h>
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#include <linux/i2c.h>
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#include <linux/list.h>
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#include <linux/workqueue.h>
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#include <linux/mutex.h>
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#include <media/v4l2-common.h>
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#include <media/v4l2-ioctl.h>
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#include <media/v4l2-device.h>
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#include <media/v4l2-fh.h>
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#include <media/videobuf2-v4l2.h>
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#include <media/videobuf2-dma-sg.h>
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#include "m00233_video_measure_memmap_package.h"
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#include "m00235_fdma_packer_memmap_package.h"
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#include "m00389_cvi_memmap_package.h"
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#include "m00460_evcnt_memmap_package.h"
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#include "m00473_freewheel_memmap_package.h"
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#include "m00479_clk_loss_detector_memmap_package.h"
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#include "m00514_syncgen_flow_evcnt_memmap_package.h"
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/* System device ID */
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#define PCI_DEVICE_ID_COBALT 0x2732
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/* Number of cobalt device nodes. */
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#define COBALT_NUM_INPUTS 4
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#define COBALT_NUM_NODES 6
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/* Number of cobalt device streams. */
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#define COBALT_NUM_STREAMS 12
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#define COBALT_HSMA_IN_NODE 4
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#define COBALT_HSMA_OUT_NODE 5
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/* Cobalt audio streams */
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#define COBALT_AUDIO_IN_STREAM 6
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#define COBALT_AUDIO_OUT_STREAM 11
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/* DMA stuff */
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#define DMA_CHANNELS_MAX 16
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/* i2c stuff */
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#define I2C_CLIENTS_MAX 16
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#define COBALT_NUM_ADAPTERS 5
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#define COBALT_CLK 50000000
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/* System status register */
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#define COBALT_SYSSTAT_DIP0_MSK (1 << 0)
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#define COBALT_SYSSTAT_DIP1_MSK (1 << 1)
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#define COBALT_SYSSTAT_HSMA_PRSNTN_MSK (1 << 2)
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#define COBALT_SYSSTAT_FLASH_RDYBSYN_MSK (1 << 3)
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#define COBALT_SYSSTAT_VI0_5V_MSK (1 << 4)
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#define COBALT_SYSSTAT_VI0_INT1_MSK (1 << 5)
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#define COBALT_SYSSTAT_VI0_INT2_MSK (1 << 6)
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#define COBALT_SYSSTAT_VI0_LOST_DATA_MSK (1 << 7)
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#define COBALT_SYSSTAT_VI1_5V_MSK (1 << 8)
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#define COBALT_SYSSTAT_VI1_INT1_MSK (1 << 9)
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#define COBALT_SYSSTAT_VI1_INT2_MSK (1 << 10)
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#define COBALT_SYSSTAT_VI1_LOST_DATA_MSK (1 << 11)
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#define COBALT_SYSSTAT_VI2_5V_MSK (1 << 12)
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#define COBALT_SYSSTAT_VI2_INT1_MSK (1 << 13)
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#define COBALT_SYSSTAT_VI2_INT2_MSK (1 << 14)
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#define COBALT_SYSSTAT_VI2_LOST_DATA_MSK (1 << 15)
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#define COBALT_SYSSTAT_VI3_5V_MSK (1 << 16)
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#define COBALT_SYSSTAT_VI3_INT1_MSK (1 << 17)
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#define COBALT_SYSSTAT_VI3_INT2_MSK (1 << 18)
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#define COBALT_SYSSTAT_VI3_LOST_DATA_MSK (1 << 19)
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#define COBALT_SYSSTAT_VIHSMA_5V_MSK (1 << 20)
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#define COBALT_SYSSTAT_VIHSMA_INT1_MSK (1 << 21)
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#define COBALT_SYSSTAT_VIHSMA_INT2_MSK (1 << 22)
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#define COBALT_SYSSTAT_VIHSMA_LOST_DATA_MSK (1 << 23)
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#define COBALT_SYSSTAT_VOHSMA_INT1_MSK (1 << 24)
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#define COBALT_SYSSTAT_VOHSMA_PLL_LOCKED_MSK (1 << 25)
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#define COBALT_SYSSTAT_VOHSMA_LOST_DATA_MSK (1 << 26)
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#define COBALT_SYSSTAT_AUD_PLL_LOCKED_MSK (1 << 28)
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#define COBALT_SYSSTAT_AUD_IN_LOST_DATA_MSK (1 << 29)
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#define COBALT_SYSSTAT_AUD_OUT_LOST_DATA_MSK (1 << 30)
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#define COBALT_SYSSTAT_PCIE_SMBCLK_MSK (1 << 31)
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/* Cobalt memory map */
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#define COBALT_I2C_0_BASE 0x0
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#define COBALT_I2C_1_BASE 0x080
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#define COBALT_I2C_2_BASE 0x100
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#define COBALT_I2C_3_BASE 0x180
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#define COBALT_I2C_HSMA_BASE 0x200
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#define COBALT_SYS_CTRL_BASE 0x400
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#define COBALT_SYS_CTRL_HSMA_TX_ENABLE_BIT 1
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#define COBALT_SYS_CTRL_VIDEO_RX_RESETN_BIT(n) (4 + 4 * (n))
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#define COBALT_SYS_CTRL_NRESET_TO_HDMI_BIT(n) (5 + 4 * (n))
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#define COBALT_SYS_CTRL_HPD_TO_CONNECTOR_BIT(n) (6 + 4 * (n))
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#define COBALT_SYS_CTRL_AUDIO_IPP_RESETN_BIT(n) (7 + 4 * (n))
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#define COBALT_SYS_CTRL_PWRDN0_TO_HSMA_TX_BIT 24
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#define COBALT_SYS_CTRL_VIDEO_TX_RESETN_BIT 25
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#define COBALT_SYS_CTRL_AUDIO_OPP_RESETN_BIT 27
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#define COBALT_SYS_STAT_BASE 0x500
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#define COBALT_SYS_STAT_MASK (COBALT_SYS_STAT_BASE + 0x08)
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#define COBALT_SYS_STAT_EDGE (COBALT_SYS_STAT_BASE + 0x0c)
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#define COBALT_HDL_INFO_BASE 0x4800
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#define COBALT_HDL_INFO_SIZE 0x200
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#define COBALT_VID_BASE 0x10000
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#define COBALT_VID_SIZE 0x1000
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#define COBALT_CVI(cobalt, c) \
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(cobalt->bar1 + COBALT_VID_BASE + (c) * COBALT_VID_SIZE)
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#define COBALT_CVI_VMR(cobalt, c) \
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(cobalt->bar1 + COBALT_VID_BASE + (c) * COBALT_VID_SIZE + 0x100)
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#define COBALT_CVI_EVCNT(cobalt, c) \
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(cobalt->bar1 + COBALT_VID_BASE + (c) * COBALT_VID_SIZE + 0x200)
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#define COBALT_CVI_FREEWHEEL(cobalt, c) \
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(cobalt->bar1 + COBALT_VID_BASE + (c) * COBALT_VID_SIZE + 0x300)
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#define COBALT_CVI_CLK_LOSS(cobalt, c) \
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(cobalt->bar1 + COBALT_VID_BASE + (c) * COBALT_VID_SIZE + 0x400)
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#define COBALT_CVI_PACKER(cobalt, c) \
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(cobalt->bar1 + COBALT_VID_BASE + (c) * COBALT_VID_SIZE + 0x500)
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#define COBALT_TX_BASE(cobalt) (cobalt->bar1 + COBALT_VID_BASE + 0x5000)
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#define DMA_INTERRUPT_STATUS_REG 0x08
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#define COBALT_HDL_SEARCH_STR "** HDL version info **"
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/* Cobalt CPU bus interface */
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#define COBALT_BUS_BAR1_BASE 0x600
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#define COBALT_BUS_SRAM_BASE 0x0
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#define COBALT_BUS_CPLD_BASE 0x00600000
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#define COBALT_BUS_FLASH_BASE 0x08000000
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/* FDMA to PCIe packing */
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#define COBALT_BYTES_PER_PIXEL_YUYV 2
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#define COBALT_BYTES_PER_PIXEL_RGB24 3
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#define COBALT_BYTES_PER_PIXEL_RGB32 4
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/* debugging */
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extern int cobalt_debug;
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extern int cobalt_ignore_err;
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#define cobalt_err(fmt, arg...) v4l2_err(&cobalt->v4l2_dev, fmt, ## arg)
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#define cobalt_warn(fmt, arg...) v4l2_warn(&cobalt->v4l2_dev, fmt, ## arg)
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#define cobalt_info(fmt, arg...) v4l2_info(&cobalt->v4l2_dev, fmt, ## arg)
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#define cobalt_dbg(level, fmt, arg...) \
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v4l2_dbg(level, cobalt_debug, &cobalt->v4l2_dev, fmt, ## arg)
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struct cobalt;
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struct cobalt_i2c_regs;
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/* Per I2C bus private algo callback data */
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struct cobalt_i2c_data {
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struct cobalt *cobalt;
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struct cobalt_i2c_regs __iomem *regs;
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};
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struct pci_consistent_buffer {
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void *virt;
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dma_addr_t bus;
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size_t bytes;
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};
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struct sg_dma_desc_info {
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void *virt;
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dma_addr_t bus;
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unsigned size;
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void *last_desc_virt;
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struct device *dev;
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};
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#define COBALT_MAX_WIDTH 1920
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#define COBALT_MAX_HEIGHT 1200
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#define COBALT_MAX_BPP 3
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#define COBALT_MAX_FRAMESZ \
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(COBALT_MAX_WIDTH * COBALT_MAX_HEIGHT * COBALT_MAX_BPP)
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#define NR_BUFS VIDEO_MAX_FRAME
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#define COBALT_STREAM_FL_DMA_IRQ 0
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#define COBALT_STREAM_FL_ADV_IRQ 1
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struct cobalt_buffer {
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struct vb2_v4l2_buffer vb;
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struct list_head list;
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};
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static inline
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struct cobalt_buffer *to_cobalt_buffer(struct vb2_v4l2_buffer *vb2)
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{
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return container_of(vb2, struct cobalt_buffer, vb);
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}
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struct cobalt_stream {
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struct video_device vdev;
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struct vb2_queue q;
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struct list_head bufs;
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struct i2c_adapter *i2c_adap;
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struct v4l2_subdev *sd;
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struct mutex lock;
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spinlock_t irqlock;
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struct v4l2_dv_timings timings;
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u32 input;
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u32 pad_source;
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u32 width, height, bpp;
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u32 stride;
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u32 pixfmt;
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u32 sequence;
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u32 colorspace;
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u32 xfer_func;
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u32 ycbcr_enc;
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u32 quantization;
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u8 dma_channel;
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int video_channel;
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unsigned dma_fifo_mask;
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unsigned adv_irq_mask;
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struct sg_dma_desc_info dma_desc_info[NR_BUFS];
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unsigned long flags;
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bool unstable_frame;
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bool enable_cvi;
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bool enable_freewheel;
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unsigned skip_first_frames;
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bool is_output;
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bool is_audio;
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bool is_dummy;
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struct cobalt *cobalt;
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struct snd_cobalt_card *alsa;
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};
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struct snd_cobalt_card;
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/* Struct to hold info about cobalt cards */
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struct cobalt {
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int instance;
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struct pci_dev *pci_dev;
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struct v4l2_device v4l2_dev;
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void __iomem *bar0, *bar1;
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u8 card_rev;
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u16 device_id;
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/* device nodes */
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struct cobalt_stream streams[DMA_CHANNELS_MAX];
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struct i2c_adapter i2c_adap[COBALT_NUM_ADAPTERS];
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struct cobalt_i2c_data i2c_data[COBALT_NUM_ADAPTERS];
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bool have_hsma_rx;
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bool have_hsma_tx;
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/* irq */
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struct workqueue_struct *irq_work_queues;
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struct work_struct irq_work_queue; /* work entry */
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/* irq counters */
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u32 irq_adv1;
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u32 irq_adv2;
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u32 irq_advout;
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u32 irq_dma_tot;
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u32 irq_dma[COBALT_NUM_STREAMS];
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u32 irq_none;
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u32 irq_full_fifo;
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/* omnitek dma */
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int dma_channels;
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int first_fifo_channel;
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bool pci_32_bit;
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char hdl_info[COBALT_HDL_INFO_SIZE];
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/* NOR flash */
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struct mtd_info *mtd;
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};
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static inline struct cobalt *to_cobalt(struct v4l2_device *v4l2_dev)
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{
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return container_of(v4l2_dev, struct cobalt, v4l2_dev);
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}
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static inline void cobalt_write_bar0(struct cobalt *cobalt, u32 reg, u32 val)
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{
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iowrite32(val, cobalt->bar0 + reg);
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}
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static inline u32 cobalt_read_bar0(struct cobalt *cobalt, u32 reg)
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{
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return ioread32(cobalt->bar0 + reg);
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}
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static inline void cobalt_write_bar1(struct cobalt *cobalt, u32 reg, u32 val)
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{
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iowrite32(val, cobalt->bar1 + reg);
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}
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static inline u32 cobalt_read_bar1(struct cobalt *cobalt, u32 reg)
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{
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return ioread32(cobalt->bar1 + reg);
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}
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static inline u32 cobalt_g_sysctrl(struct cobalt *cobalt)
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{
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return cobalt_read_bar1(cobalt, COBALT_SYS_CTRL_BASE);
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}
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static inline void cobalt_s_bit_sysctrl(struct cobalt *cobalt,
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int bit, int val)
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{
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u32 ctrl = cobalt_read_bar1(cobalt, COBALT_SYS_CTRL_BASE);
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cobalt_write_bar1(cobalt, COBALT_SYS_CTRL_BASE,
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(ctrl & ~(1UL << bit)) | (val << bit));
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}
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static inline u32 cobalt_g_sysstat(struct cobalt *cobalt)
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{
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return cobalt_read_bar1(cobalt, COBALT_SYS_STAT_BASE);
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}
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#define ADRS_REG (bar1 + COBALT_BUS_BAR1_BASE + 0)
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#define LOWER_DATA (bar1 + COBALT_BUS_BAR1_BASE + 4)
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#define UPPER_DATA (bar1 + COBALT_BUS_BAR1_BASE + 6)
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static inline u32 cobalt_bus_read32(void __iomem *bar1, u32 bus_adrs)
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{
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iowrite32(bus_adrs, ADRS_REG);
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return ioread32(LOWER_DATA);
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}
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static inline void cobalt_bus_write16(void __iomem *bar1,
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u32 bus_adrs, u16 data)
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{
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iowrite32(bus_adrs, ADRS_REG);
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if (bus_adrs & 2)
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iowrite16(data, UPPER_DATA);
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else
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iowrite16(data, LOWER_DATA);
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}
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static inline void cobalt_bus_write32(void __iomem *bar1,
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u32 bus_adrs, u16 data)
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{
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iowrite32(bus_adrs, ADRS_REG);
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if (bus_adrs & 2)
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iowrite32(data, UPPER_DATA);
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else
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iowrite32(data, LOWER_DATA);
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}
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/*==============Prototypes==================*/
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void cobalt_pcie_status_show(struct cobalt *cobalt);
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#endif
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