forked from mirrors/linux
0b8439d374
- Move IRQ register address computation inside macros (Kishon Vijay
Abraham I)
- Separate legacy IRQ and MSI configuration (Kishon Vijay Abraham I)
- Use hwirq, not virq, to get MSI IRQ number offset (Kishon Vijay Abraham
I)
- Squash ks_pcie_handle_msi_irq() into ks_pcie_msi_irq_handler() (Kishon
Vijay Abraham I)
- Add dwc support for platforms with custom MSI controllers (Kishon Vijay
Abraham I)
- Add keystone-specific MSI controller (Kishon Vijay Abraham I)
- Remove dwc host_ops previously used for keystone-specific MSI (Kishon
Vijay Abraham I)
- Skip dwc default MSI init if platform has custom MSI controller (Kishon
Vijay Abraham I)
- Implement .start_link() and .stop_link() for keystone endpoint support
(Kishon Vijay Abraham I)
- Add keystone "reg-names" DT binding (Kishon Vijay Abraham I)
- Squash ks_pcie_dw_host_init() into ks_pcie_add_pcie_port() (Kishon
Vijay Abraham I)
- Get keystone register resources from DT by name, not index (Kishon
Vijay Abraham I)
- Get DT resources in .probe() to prepare for endpoint support (Kishon
Vijay Abraham I)
- Add "ti,syscon-pcie-mode" DT property for PCIe mode configuration
(Kishon Vijay Abraham I)
- Explicitly set keystone to host mode (Kishon Vijay Abraham I)
- Document DT "atu" reg-names requirement for DesignWare core >= 4.80
(Kishon Vijay Abraham I)
- Enable dwc iATU unroll for endpoint mode as well as host mode (Kishon
Vijay Abraham I)
- Add dwc "version" to identify core >= 4.80 for ATU programming (Kishon
Vijay Abraham I)
- Don't build ARM32-specific keystone code on ARM64 (Kishon Vijay Abraham
I)
- Add DT binding for keystone PCIe RC in AM654 SoC (Kishon Vijay Abraham
I)
- Add keystone support for AM654 SoC PCIe RC (Kishon Vijay Abraham I)
- Reset keystone PHYs before enabling them (Kishon Vijay Abraham I)
- Make of_pci_get_max_link_speed() available to endpoint drivers as well
as host drivers (Kishon Vijay Abraham I)
- Add keystone support for DT "max-link-speed" property (Kishon Vijay
Abraham I)
- Add endpoint library support for BAR buffer alignment (Kishon Vijay
Abraham I)
- Make all dw_pcie_ep_ops structs const (Kishon Vijay Abraham I)
- Fix fencepost error in dw_pcie_ep_find_capability() (Kishon Vijay
Abraham I)
- Add dwc hooks for dbi/dbi2 that share the same address space (Kishon
Vijay Abraham I)
- Add keystone support for TI AM654x in endpoint mode (Kishon Vijay
Abraham I)
- Configure designware endpoints to advertise smallest resizable BAR
(1MB) (Kishon Vijay Abraham I)
- Align designware endpoint ATU windows for raising MSIs (Kishon Vijay
Abraham I)
- Add endpoint test support for TI AM654x (Kishon Vijay Abraham I)
- Fix endpoint test test_reg_bar issue (Kishon Vijay Abraham I)
* remotes/lorenzo/pci/keystone:
misc: pci_endpoint_test: Fix test_reg_bar to be updated in pci_endpoint_test
misc: pci_endpoint_test: Add support to test PCI EP in AM654x
PCI: designware-ep: Use aligned ATU window for raising MSI interrupts
PCI: designware-ep: Configure Resizable BAR cap to advertise the smallest size
PCI: keystone: Add support for PCIe EP in AM654x Platforms
dt-bindings: PCI: Add PCI EP DT binding documentation for AM654
PCI: dwc: Add callbacks for accessing dbi2 address space
PCI: dwc: Fix dw_pcie_ep_find_capability() to return correct capability offset
PCI: dwc: Add const qualifier to struct dw_pcie_ep_ops
PCI: endpoint: Add support to specify alignment for buffers allocated to BARs
PCI: keystone: Add support to set the max link speed from DT
PCI: OF: Allow of_pci_get_max_link_speed() to be used by PCI Endpoint drivers
PCI: keystone: Invoke phy_reset() API before enabling PHY
PCI: keystone: Add support for PCIe RC in AM654x Platforms
dt-bindings: PCI: Add PCI RC DT binding documentation for AM654
PCI: keystone: Prevent ARM32 specific code to be compiled for ARM64
PCI: dwc: Fix ATU identification for designware version >= 4.80
PCI: dwc: Enable iATU unroll for endpoint too
dt-bindings: PCI: Document "atu" reg-names
PCI: keystone: Explicitly set the PCIe mode
dt-bindings: PCI: Add dt-binding to configure PCIe mode
PCI: keystone: Move resources initialization to prepare for EP support
PCI: keystone: Use platform_get_resource_byname() to get memory resources
PCI: keystone: Perform host initialization in a single function
dt-bindings: PCI: keystone: Add "reg-names" binding information
PCI: keystone: Cleanup error_irq configuration
PCI: keystone: Add start_link()/stop_link() dw_pcie_ops
PCI: dwc: Remove default MSI initialization for platform specific MSI chips
PCI: dwc: Remove Keystone specific dw_pcie_host_ops
PCI: keystone: Use Keystone specific msi_irq_chip
PCI: dwc: Add support to use non default msi_irq_chip
PCI: keystone: Cleanup ks_pcie_msi_irq_handler()
PCI: keystone: Use hwirq to get the MSI IRQ number offset
PCI: keystone: Add separate functions for configuring MSI and legacy interrupt
PCI: keystone: Cleanup interrupt related macros
# Conflicts:
# drivers/pci/controller/dwc/pcie-designware.h
429 lines
12 KiB
C
429 lines
12 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Synopsys DesignWare PCIe host controller driver
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*
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* Copyright (C) 2013 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Author: Jingoo Han <jg1.han@samsung.com>
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*/
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#ifndef _PCIE_DESIGNWARE_H
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#define _PCIE_DESIGNWARE_H
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#include <linux/bitfield.h>
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#include <linux/dma-mapping.h>
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#include <linux/irq.h>
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#include <linux/msi.h>
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#include <linux/pci.h>
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#include <linux/pci-epc.h>
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#include <linux/pci-epf.h>
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/* Parameters for the waiting for link up routine */
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#define LINK_WAIT_MAX_RETRIES 10
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#define LINK_WAIT_USLEEP_MIN 90000
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#define LINK_WAIT_USLEEP_MAX 100000
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/* Parameters for the waiting for iATU enabled routine */
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#define LINK_WAIT_MAX_IATU_RETRIES 5
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#define LINK_WAIT_IATU 9
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/* Synopsys-specific PCIe configuration registers */
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#define PCIE_PORT_LINK_CONTROL 0x710
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#define PORT_LINK_MODE_MASK GENMASK(21, 16)
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#define PORT_LINK_MODE(n) FIELD_PREP(PORT_LINK_MODE_MASK, n)
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#define PORT_LINK_MODE_1_LANES PORT_LINK_MODE(0x1)
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#define PORT_LINK_MODE_2_LANES PORT_LINK_MODE(0x3)
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#define PORT_LINK_MODE_4_LANES PORT_LINK_MODE(0x7)
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#define PORT_LINK_MODE_8_LANES PORT_LINK_MODE(0xf)
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#define PCIE_PORT_DEBUG0 0x728
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#define PORT_LOGIC_LTSSM_STATE_MASK 0x1f
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#define PORT_LOGIC_LTSSM_STATE_L0 0x11
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#define PCIE_PORT_DEBUG1 0x72C
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#define PCIE_PORT_DEBUG1_LINK_UP BIT(4)
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#define PCIE_PORT_DEBUG1_LINK_IN_TRAINING BIT(29)
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#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
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#define PORT_LOGIC_SPEED_CHANGE BIT(17)
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#define PORT_LOGIC_LINK_WIDTH_MASK GENMASK(12, 8)
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#define PORT_LOGIC_LINK_WIDTH(n) FIELD_PREP(PORT_LOGIC_LINK_WIDTH_MASK, n)
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#define PORT_LOGIC_LINK_WIDTH_1_LANES PORT_LOGIC_LINK_WIDTH(0x1)
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#define PORT_LOGIC_LINK_WIDTH_2_LANES PORT_LOGIC_LINK_WIDTH(0x2)
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#define PORT_LOGIC_LINK_WIDTH_4_LANES PORT_LOGIC_LINK_WIDTH(0x4)
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#define PORT_LOGIC_LINK_WIDTH_8_LANES PORT_LOGIC_LINK_WIDTH(0x8)
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#define PCIE_MSI_ADDR_LO 0x820
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#define PCIE_MSI_ADDR_HI 0x824
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#define PCIE_MSI_INTR0_ENABLE 0x828
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#define PCIE_MSI_INTR0_MASK 0x82C
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#define PCIE_MSI_INTR0_STATUS 0x830
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#define PCIE_ATU_VIEWPORT 0x900
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#define PCIE_ATU_REGION_INBOUND BIT(31)
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#define PCIE_ATU_REGION_OUTBOUND 0
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#define PCIE_ATU_REGION_INDEX2 0x2
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#define PCIE_ATU_REGION_INDEX1 0x1
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#define PCIE_ATU_REGION_INDEX0 0x0
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#define PCIE_ATU_CR1 0x904
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#define PCIE_ATU_TYPE_MEM 0x0
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#define PCIE_ATU_TYPE_IO 0x2
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#define PCIE_ATU_TYPE_CFG0 0x4
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#define PCIE_ATU_TYPE_CFG1 0x5
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#define PCIE_ATU_CR2 0x908
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#define PCIE_ATU_ENABLE BIT(31)
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#define PCIE_ATU_BAR_MODE_ENABLE BIT(30)
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#define PCIE_ATU_LOWER_BASE 0x90C
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#define PCIE_ATU_UPPER_BASE 0x910
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#define PCIE_ATU_LIMIT 0x914
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#define PCIE_ATU_LOWER_TARGET 0x918
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#define PCIE_ATU_BUS(x) FIELD_PREP(GENMASK(31, 24), x)
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#define PCIE_ATU_DEV(x) FIELD_PREP(GENMASK(23, 19), x)
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#define PCIE_ATU_FUNC(x) FIELD_PREP(GENMASK(18, 16), x)
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#define PCIE_ATU_UPPER_TARGET 0x91C
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#define PCIE_MISC_CONTROL_1_OFF 0x8BC
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#define PCIE_DBI_RO_WR_EN BIT(0)
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/*
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* iATU Unroll-specific register definitions
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* From 4.80 core version the address translation will be made by unroll
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*/
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#define PCIE_ATU_UNR_REGION_CTRL1 0x00
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#define PCIE_ATU_UNR_REGION_CTRL2 0x04
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#define PCIE_ATU_UNR_LOWER_BASE 0x08
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#define PCIE_ATU_UNR_UPPER_BASE 0x0C
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#define PCIE_ATU_UNR_LIMIT 0x10
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#define PCIE_ATU_UNR_LOWER_TARGET 0x14
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#define PCIE_ATU_UNR_UPPER_TARGET 0x18
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/*
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* The default address offset between dbi_base and atu_base. Root controller
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* drivers are not required to initialize atu_base if the offset matches this
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* default; the driver core automatically derives atu_base from dbi_base using
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* this offset, if atu_base not set.
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*/
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#define DEFAULT_DBI_ATU_OFFSET (0x3 << 20)
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/* Register address builder */
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#define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region) \
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((region) << 9)
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#define PCIE_GET_ATU_INB_UNR_REG_OFFSET(region) \
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(((region) << 9) | BIT(8))
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#define MAX_MSI_IRQS 256
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#define MAX_MSI_IRQS_PER_CTRL 32
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#define MAX_MSI_CTRLS (MAX_MSI_IRQS / MAX_MSI_IRQS_PER_CTRL)
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#define MSI_REG_CTRL_BLOCK_SIZE 12
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#define MSI_DEF_NUM_VECTORS 32
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/* Maximum number of inbound/outbound iATUs */
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#define MAX_IATU_IN 256
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#define MAX_IATU_OUT 256
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struct pcie_port;
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struct dw_pcie;
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struct dw_pcie_ep;
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enum dw_pcie_region_type {
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DW_PCIE_REGION_UNKNOWN,
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DW_PCIE_REGION_INBOUND,
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DW_PCIE_REGION_OUTBOUND,
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};
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enum dw_pcie_device_mode {
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DW_PCIE_UNKNOWN_TYPE,
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DW_PCIE_EP_TYPE,
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DW_PCIE_LEG_EP_TYPE,
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DW_PCIE_RC_TYPE,
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};
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struct dw_pcie_host_ops {
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int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val);
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int (*wr_own_conf)(struct pcie_port *pp, int where, int size, u32 val);
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int (*rd_other_conf)(struct pcie_port *pp, struct pci_bus *bus,
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unsigned int devfn, int where, int size, u32 *val);
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int (*wr_other_conf)(struct pcie_port *pp, struct pci_bus *bus,
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unsigned int devfn, int where, int size, u32 val);
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int (*host_init)(struct pcie_port *pp);
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void (*scan_bus)(struct pcie_port *pp);
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void (*set_num_vectors)(struct pcie_port *pp);
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int (*msi_host_init)(struct pcie_port *pp);
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};
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struct pcie_port {
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u8 root_bus_nr;
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u64 cfg0_base;
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void __iomem *va_cfg0_base;
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u32 cfg0_size;
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u64 cfg1_base;
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void __iomem *va_cfg1_base;
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u32 cfg1_size;
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resource_size_t io_base;
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phys_addr_t io_bus_addr;
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u32 io_size;
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u64 mem_base;
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phys_addr_t mem_bus_addr;
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u32 mem_size;
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struct resource *cfg;
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struct resource *io;
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struct resource *mem;
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struct resource *busn;
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int irq;
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const struct dw_pcie_host_ops *ops;
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int msi_irq;
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struct irq_domain *irq_domain;
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struct irq_domain *msi_domain;
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dma_addr_t msi_data;
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struct page *msi_page;
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struct irq_chip *msi_irq_chip;
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u32 num_vectors;
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u32 irq_mask[MAX_MSI_CTRLS];
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struct pci_bus *root_bus;
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raw_spinlock_t lock;
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DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS);
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};
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enum dw_pcie_as_type {
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DW_PCIE_AS_UNKNOWN,
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DW_PCIE_AS_MEM,
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DW_PCIE_AS_IO,
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};
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struct dw_pcie_ep_ops {
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void (*ep_init)(struct dw_pcie_ep *ep);
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int (*raise_irq)(struct dw_pcie_ep *ep, u8 func_no,
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enum pci_epc_irq_type type, u16 interrupt_num);
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const struct pci_epc_features* (*get_features)(struct dw_pcie_ep *ep);
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};
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struct dw_pcie_ep {
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struct pci_epc *epc;
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const struct dw_pcie_ep_ops *ops;
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phys_addr_t phys_base;
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size_t addr_size;
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size_t page_size;
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u8 bar_to_atu[6];
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phys_addr_t *outbound_addr;
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unsigned long *ib_window_map;
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unsigned long *ob_window_map;
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u32 num_ib_windows;
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u32 num_ob_windows;
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void __iomem *msi_mem;
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phys_addr_t msi_mem_phys;
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u8 msi_cap; /* MSI capability offset */
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u8 msix_cap; /* MSI-X capability offset */
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};
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struct dw_pcie_ops {
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u64 (*cpu_addr_fixup)(struct dw_pcie *pcie, u64 cpu_addr);
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u32 (*read_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg,
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size_t size);
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void (*write_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg,
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size_t size, u32 val);
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u32 (*read_dbi2)(struct dw_pcie *pcie, void __iomem *base, u32 reg,
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size_t size);
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void (*write_dbi2)(struct dw_pcie *pcie, void __iomem *base, u32 reg,
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size_t size, u32 val);
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int (*link_up)(struct dw_pcie *pcie);
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int (*start_link)(struct dw_pcie *pcie);
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void (*stop_link)(struct dw_pcie *pcie);
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};
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struct dw_pcie {
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struct device *dev;
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void __iomem *dbi_base;
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void __iomem *dbi_base2;
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/* Used when iatu_unroll_enabled is true */
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void __iomem *atu_base;
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u32 num_viewport;
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u8 iatu_unroll_enabled;
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struct pcie_port pp;
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struct dw_pcie_ep ep;
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const struct dw_pcie_ops *ops;
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unsigned int version;
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};
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#define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp)
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#define to_dw_pcie_from_ep(endpoint) \
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container_of((endpoint), struct dw_pcie, ep)
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int dw_pcie_read(void __iomem *addr, int size, u32 *val);
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int dw_pcie_write(void __iomem *addr, int size, u32 val);
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u32 __dw_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
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size_t size);
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void __dw_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
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size_t size, u32 val);
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u32 __dw_pcie_read_dbi2(struct dw_pcie *pci, void __iomem *base, u32 reg,
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size_t size);
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void __dw_pcie_write_dbi2(struct dw_pcie *pci, void __iomem *base, u32 reg,
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size_t size, u32 val);
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int dw_pcie_link_up(struct dw_pcie *pci);
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int dw_pcie_wait_for_link(struct dw_pcie *pci);
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void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index,
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int type, u64 cpu_addr, u64 pci_addr,
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u32 size);
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int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int bar,
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u64 cpu_addr, enum dw_pcie_as_type as_type);
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void dw_pcie_disable_atu(struct dw_pcie *pci, int index,
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enum dw_pcie_region_type type);
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void dw_pcie_setup(struct dw_pcie *pci);
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static inline void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val)
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{
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__dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x4, val);
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}
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static inline u32 dw_pcie_readl_dbi(struct dw_pcie *pci, u32 reg)
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{
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return __dw_pcie_read_dbi(pci, pci->dbi_base, reg, 0x4);
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}
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static inline void dw_pcie_writew_dbi(struct dw_pcie *pci, u32 reg, u16 val)
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{
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__dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x2, val);
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}
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static inline u16 dw_pcie_readw_dbi(struct dw_pcie *pci, u32 reg)
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{
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return __dw_pcie_read_dbi(pci, pci->dbi_base, reg, 0x2);
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}
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static inline void dw_pcie_writeb_dbi(struct dw_pcie *pci, u32 reg, u8 val)
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{
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__dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x1, val);
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}
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static inline u8 dw_pcie_readb_dbi(struct dw_pcie *pci, u32 reg)
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{
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return __dw_pcie_read_dbi(pci, pci->dbi_base, reg, 0x1);
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}
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static inline void dw_pcie_writel_dbi2(struct dw_pcie *pci, u32 reg, u32 val)
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{
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__dw_pcie_write_dbi2(pci, pci->dbi_base2, reg, 0x4, val);
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}
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static inline u32 dw_pcie_readl_dbi2(struct dw_pcie *pci, u32 reg)
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{
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return __dw_pcie_read_dbi2(pci, pci->dbi_base2, reg, 0x4);
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}
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static inline void dw_pcie_writel_atu(struct dw_pcie *pci, u32 reg, u32 val)
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{
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__dw_pcie_write_dbi(pci, pci->atu_base, reg, 0x4, val);
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}
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static inline u32 dw_pcie_readl_atu(struct dw_pcie *pci, u32 reg)
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{
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return __dw_pcie_read_dbi(pci, pci->atu_base, reg, 0x4);
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}
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static inline void dw_pcie_dbi_ro_wr_en(struct dw_pcie *pci)
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{
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u32 reg;
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u32 val;
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reg = PCIE_MISC_CONTROL_1_OFF;
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val = dw_pcie_readl_dbi(pci, reg);
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val |= PCIE_DBI_RO_WR_EN;
|
|
dw_pcie_writel_dbi(pci, reg, val);
|
|
}
|
|
|
|
static inline void dw_pcie_dbi_ro_wr_dis(struct dw_pcie *pci)
|
|
{
|
|
u32 reg;
|
|
u32 val;
|
|
|
|
reg = PCIE_MISC_CONTROL_1_OFF;
|
|
val = dw_pcie_readl_dbi(pci, reg);
|
|
val &= ~PCIE_DBI_RO_WR_EN;
|
|
dw_pcie_writel_dbi(pci, reg, val);
|
|
}
|
|
|
|
#ifdef CONFIG_PCIE_DW_HOST
|
|
irqreturn_t dw_handle_msi_irq(struct pcie_port *pp);
|
|
void dw_pcie_msi_init(struct pcie_port *pp);
|
|
void dw_pcie_free_msi(struct pcie_port *pp);
|
|
void dw_pcie_setup_rc(struct pcie_port *pp);
|
|
int dw_pcie_host_init(struct pcie_port *pp);
|
|
int dw_pcie_allocate_domains(struct pcie_port *pp);
|
|
#else
|
|
static inline irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
|
|
{
|
|
return IRQ_NONE;
|
|
}
|
|
|
|
static inline void dw_pcie_msi_init(struct pcie_port *pp)
|
|
{
|
|
}
|
|
|
|
static inline void dw_pcie_free_msi(struct pcie_port *pp)
|
|
{
|
|
}
|
|
|
|
static inline void dw_pcie_setup_rc(struct pcie_port *pp)
|
|
{
|
|
}
|
|
|
|
static inline int dw_pcie_host_init(struct pcie_port *pp)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline int dw_pcie_allocate_domains(struct pcie_port *pp)
|
|
{
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_PCIE_DW_EP
|
|
void dw_pcie_ep_linkup(struct dw_pcie_ep *ep);
|
|
int dw_pcie_ep_init(struct dw_pcie_ep *ep);
|
|
void dw_pcie_ep_exit(struct dw_pcie_ep *ep);
|
|
int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no);
|
|
int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
|
|
u8 interrupt_num);
|
|
int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
|
|
u16 interrupt_num);
|
|
void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar);
|
|
#else
|
|
static inline void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
|
|
{
|
|
}
|
|
|
|
static inline int dw_pcie_ep_init(struct dw_pcie_ep *ep)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
|
|
{
|
|
}
|
|
|
|
static inline int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
|
|
u8 interrupt_num)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
|
|
u16 interrupt_num)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
|
|
{
|
|
}
|
|
#endif
|
|
#endif /* _PCIE_DESIGNWARE_H */
|