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			Commitc3b8e884de("platform/x86: intel_int0002_vgpio: Implement irq_set_wake"), was written to fix some wakeup issues on Bay Trail (BYT) devices. We've received a bug report that this causes a suspend regression on some Cherry Trail (CHT) based devices. To fix the issues this causes on CHT devices, this commit modifies the irq_set_wake support so that we only implement irq_set_wake on BYT devices, Fixes:c3b8e884de("platform/x86: intel_int0002_vgpio: ... irq_set_wake") Reported-and-tested-by: Maxim Mikityanskiy <maxtram95@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
		
			
				
	
	
		
			248 lines
		
	
	
	
		
			6.3 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			248 lines
		
	
	
	
		
			6.3 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| // SPDX-License-Identifier: GPL-2.0
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| /*
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|  * Intel INT0002 "Virtual GPIO" driver
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|  *
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|  * Copyright (C) 2017 Hans de Goede <hdegoede@redhat.com>
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|  *
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|  * Loosely based on android x86 kernel code which is:
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|  *
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|  * Copyright (c) 2014, Intel Corporation.
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|  *
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|  * Author: Dyut Kumar Sil <dyut.k.sil@intel.com>
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|  *
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|  * Some peripherals on Bay Trail and Cherry Trail platforms signal a Power
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|  * Management Event (PME) to the Power Management Controller (PMC) to wakeup
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|  * the system. When this happens software needs to clear the PME bus 0 status
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|  * bit in the GPE0a_STS register to avoid an IRQ storm on IRQ 9.
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|  *
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|  * This is modelled in ACPI through the INT0002 ACPI device, which is
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|  * called a "Virtual GPIO controller" in ACPI because it defines the event
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|  * handler to call when the PME triggers through _AEI and _L02 / _E02
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|  * methods as would be done for a real GPIO interrupt in ACPI. Note this
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|  * is a hack to define an AML event handler for the PME while using existing
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|  * ACPI mechanisms, this is not a real GPIO at all.
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|  *
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|  * This driver will bind to the INT0002 device, and register as a GPIO
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|  * controller, letting gpiolib-acpi.c call the _L02 handler as it would
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|  * for a real GPIO controller.
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|  */
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| 
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| #include <linux/acpi.h>
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| #include <linux/bitmap.h>
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| #include <linux/gpio/driver.h>
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| #include <linux/interrupt.h>
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| #include <linux/io.h>
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| #include <linux/kernel.h>
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| #include <linux/module.h>
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| #include <linux/platform_device.h>
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| #include <linux/slab.h>
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| #include <linux/suspend.h>
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| 
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| #include <asm/cpu_device_id.h>
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| #include <asm/intel-family.h>
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| 
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| #define DRV_NAME			"INT0002 Virtual GPIO"
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| 
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| /* For some reason the virtual GPIO pin tied to the GPE is numbered pin 2 */
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| #define GPE0A_PME_B0_VIRT_GPIO_PIN	2
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| 
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| #define GPE0A_PME_B0_STS_BIT		BIT(13)
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| #define GPE0A_PME_B0_EN_BIT		BIT(13)
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| #define GPE0A_STS_PORT			0x420
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| #define GPE0A_EN_PORT			0x428
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| 
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| #define BAYTRAIL			0x01
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| #define CHERRYTRAIL			0x02
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| 
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| #define ICPU(model, data) { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, data }
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| 
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| static const struct x86_cpu_id int0002_cpu_ids[] = {
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| 	ICPU(INTEL_FAM6_ATOM_SILVERMONT, BAYTRAIL), /* Valleyview, Bay Trail  */
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| 	ICPU(INTEL_FAM6_ATOM_AIRMONT, CHERRYTRAIL), /* Braswell, Cherry Trail */
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| 	{}
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| };
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| 
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| /*
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|  * As this is not a real GPIO at all, but just a hack to model an event in
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|  * ACPI the get / set functions are dummy functions.
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|  */
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| 
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| static int int0002_gpio_get(struct gpio_chip *chip, unsigned int offset)
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| {
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| 	return 0;
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| }
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| 
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| static void int0002_gpio_set(struct gpio_chip *chip, unsigned int offset,
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| 			     int value)
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| {
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| }
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| 
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| static int int0002_gpio_direction_output(struct gpio_chip *chip,
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| 					 unsigned int offset, int value)
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| {
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| 	return 0;
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| }
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| 
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| static void int0002_irq_ack(struct irq_data *data)
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| {
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| 	outl(GPE0A_PME_B0_STS_BIT, GPE0A_STS_PORT);
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| }
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| 
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| static void int0002_irq_unmask(struct irq_data *data)
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| {
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| 	u32 gpe_en_reg;
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| 
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| 	gpe_en_reg = inl(GPE0A_EN_PORT);
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| 	gpe_en_reg |= GPE0A_PME_B0_EN_BIT;
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| 	outl(gpe_en_reg, GPE0A_EN_PORT);
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| }
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| 
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| static void int0002_irq_mask(struct irq_data *data)
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| {
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| 	u32 gpe_en_reg;
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| 
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| 	gpe_en_reg = inl(GPE0A_EN_PORT);
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| 	gpe_en_reg &= ~GPE0A_PME_B0_EN_BIT;
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| 	outl(gpe_en_reg, GPE0A_EN_PORT);
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| }
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| 
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| static int int0002_irq_set_wake(struct irq_data *data, unsigned int on)
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| {
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| 	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
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| 	struct platform_device *pdev = to_platform_device(chip->parent);
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| 	int irq = platform_get_irq(pdev, 0);
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| 
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| 	/* Propagate to parent irq */
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| 	if (on)
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| 		enable_irq_wake(irq);
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| 	else
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| 		disable_irq_wake(irq);
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| 
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| 	return 0;
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| }
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| 
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| static irqreturn_t int0002_irq(int irq, void *data)
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| {
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| 	struct gpio_chip *chip = data;
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| 	u32 gpe_sts_reg;
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| 
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| 	gpe_sts_reg = inl(GPE0A_STS_PORT);
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| 	if (!(gpe_sts_reg & GPE0A_PME_B0_STS_BIT))
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| 		return IRQ_NONE;
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| 
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| 	generic_handle_irq(irq_find_mapping(chip->irq.domain,
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| 					    GPE0A_PME_B0_VIRT_GPIO_PIN));
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| 
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| 	pm_system_wakeup();
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| 
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| 	return IRQ_HANDLED;
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| }
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| 
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| static struct irq_chip int0002_byt_irqchip = {
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| 	.name			= DRV_NAME,
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| 	.irq_ack		= int0002_irq_ack,
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| 	.irq_mask		= int0002_irq_mask,
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| 	.irq_unmask		= int0002_irq_unmask,
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| 	.irq_set_wake		= int0002_irq_set_wake,
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| };
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| 
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| static struct irq_chip int0002_cht_irqchip = {
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| 	.name			= DRV_NAME,
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| 	.irq_ack		= int0002_irq_ack,
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| 	.irq_mask		= int0002_irq_mask,
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| 	.irq_unmask		= int0002_irq_unmask,
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| 	/*
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| 	 * No set_wake, on CHT the IRQ is typically shared with the ACPI SCI
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| 	 * and we don't want to mess with the ACPI SCI irq settings.
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| 	 */
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| };
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| 
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| static int int0002_probe(struct platform_device *pdev)
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| {
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| 	struct device *dev = &pdev->dev;
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| 	const struct x86_cpu_id *cpu_id;
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| 	struct irq_chip *irq_chip;
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| 	struct gpio_chip *chip;
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| 	int irq, ret;
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| 
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| 	/* Menlow has a different INT0002 device? <sigh> */
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| 	cpu_id = x86_match_cpu(int0002_cpu_ids);
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| 	if (!cpu_id)
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| 		return -ENODEV;
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| 
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| 	irq = platform_get_irq(pdev, 0);
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| 	if (irq < 0) {
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| 		dev_err(dev, "Error getting IRQ: %d\n", irq);
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| 		return irq;
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| 	}
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| 
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| 	chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
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| 	if (!chip)
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| 		return -ENOMEM;
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| 
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| 	chip->label = DRV_NAME;
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| 	chip->parent = dev;
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| 	chip->owner = THIS_MODULE;
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| 	chip->get = int0002_gpio_get;
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| 	chip->set = int0002_gpio_set;
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| 	chip->direction_input = int0002_gpio_get;
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| 	chip->direction_output = int0002_gpio_direction_output;
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| 	chip->base = -1;
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| 	chip->ngpio = GPE0A_PME_B0_VIRT_GPIO_PIN + 1;
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| 	chip->irq.need_valid_mask = true;
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| 
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| 	ret = devm_gpiochip_add_data(&pdev->dev, chip, NULL);
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| 	if (ret) {
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| 		dev_err(dev, "Error adding gpio chip: %d\n", ret);
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| 		return ret;
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| 	}
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| 
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| 	bitmap_clear(chip->irq.valid_mask, 0, GPE0A_PME_B0_VIRT_GPIO_PIN);
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| 
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| 	/*
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| 	 * We manually request the irq here instead of passing a flow-handler
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| 	 * to gpiochip_set_chained_irqchip, because the irq is shared.
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| 	 */
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| 	ret = devm_request_irq(dev, irq, int0002_irq,
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| 			       IRQF_SHARED, "INT0002", chip);
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| 	if (ret) {
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| 		dev_err(dev, "Error requesting IRQ %d: %d\n", irq, ret);
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| 		return ret;
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| 	}
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| 
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| 	if (cpu_id->driver_data == BAYTRAIL)
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| 		irq_chip = &int0002_byt_irqchip;
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| 	else
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| 		irq_chip = &int0002_cht_irqchip;
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| 
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| 	ret = gpiochip_irqchip_add(chip, irq_chip, 0, handle_edge_irq,
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| 				   IRQ_TYPE_NONE);
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| 	if (ret) {
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| 		dev_err(dev, "Error adding irqchip: %d\n", ret);
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| 		return ret;
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| 	}
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| 
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| 	gpiochip_set_chained_irqchip(chip, irq_chip, irq, NULL);
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| 
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| 	return 0;
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| }
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| 
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| static const struct acpi_device_id int0002_acpi_ids[] = {
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| 	{ "INT0002", 0 },
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| 	{ },
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| };
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| MODULE_DEVICE_TABLE(acpi, int0002_acpi_ids);
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| 
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| static struct platform_driver int0002_driver = {
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| 	.driver = {
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| 		.name			= DRV_NAME,
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| 		.acpi_match_table	= int0002_acpi_ids,
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| 	},
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| 	.probe	= int0002_probe,
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| };
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| 
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| module_platform_driver(int0002_driver);
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| 
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| MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>");
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| MODULE_DESCRIPTION("Intel INT0002 Virtual GPIO driver");
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| MODULE_LICENSE("GPL v2");
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