Ilya Bakoulin df60dcf5b5 drm/amd/display: Add 3DLUT FL HW bug workaround ... [Why] There is a known HW bug that causes the internal 3DLUT fetch signal to be lost at VREADY, regardless of whether the OTG lock is being held or not. A workaround is necessary to make sure that this internal signal stays up after OTG unlock. [How] Set the 3DLUT_ENABLE bit immediately before and after the unlock. Also use VUPDATE_KEEPOUT to prevent lock transition in the region between VSTARTUP and VREADY, which could cause issues with this WA sequence. Also including misc. 3DLUT DMA-related sequence fixes to address a few regressions causing corruption. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2024-10-15 11:23:12 -04:00
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hw	drm/amd/display: Add 3DLUT FL HW bug workaround	2024-10-15 11:23:12 -04:00
bw_fixed.h
clock_source.h	drm/amd/display: Refactor input mode programming for DIG FIFO	2024-05-08 14:57:04 -04:00
compressor.h
core_status.h
core_types.h	drm/amd/display: Update Interface to Check UCLK DPM	2024-10-07 14:16:44 -04:00
custom_float.h
dce_calcs.h
dcn_calc_math.h
dcn_calcs.h	drm/amd/display: Includes adjustments	2024-04-09 22:07:09 -04:00
link.h	drm/amd/display: Extend PSRSU residency mode	2024-06-14 15:20:40 -04:00
link_enc_cfg.h
link_hwss.h
reg_helper.h
resource.h	drm/amd/display: Update HPO I/O When Handling Link Retrain Automation Request	2024-08-20 22:14:13 -04:00
vm_helper.h